Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

Abstract: A light emitting diode includes an active layer, a first type semiconductor layer, a second type semiconductor layer, a coupling layer, and a sacrificial thin film. The first type semiconductor layer and the second type semiconductor layer are disposed at opposite sides of the active layer. The coupling layer is disposed on the second type semiconductor layer. The sacrificial thin film is disposed on the coupling layer, in which the coupling layer is disposed between the sacrificial thin film and the second type semiconductor layer, and the sacrificial thin film has a thickness less than a total thickness of the first type semiconductor layer, the active layer, the second type semiconductor layer and the coupling layer.

Abstract: The present disclosure, in some embodiments, relates to a photolithography tool. The photolithography tool includes a source configured to generate electromagnetic radiation. A dynamic focal system is configured to provide the electromagnetic radiation to a plurality of different vertical positions over a substrate stage. The plurality of different vertical positions include a first position having a first depth of focus and a second position having a second depth of focus that is below the first depth of focus and that vertically overlaps the first depth of focus.

Abstract: Systems and methods for performing reflow modeling in a virtual fabrication environment are discussed. More particularly, the virtual fabrication environment may determine metal or material “reflow” or movement during fabrication of a semiconductor device structure. A reflow modeling step with user-specified parameters may be inserted into a process sequence used during fabrication of the semiconductor device structure.

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

Abstract: Methods of ion implantation combined with annealing using a pulsed laser or a furnace for cutting substrate in forming semiconductor devices and semiconductor devices including the same are disclosed. In an embodiment, a method includes forming a transistor structure of a device on a first semiconductor substrate; forming a front-side interconnect structure over a front side of the transistor structure; bonding a carrier substrate to the front-side interconnect structure; implanting ions into the first semiconductor substrate to form an implantation region of the first semiconductor substrate; and removing the first semiconductor substrate. Removing the first semiconductor substrate includes applying an annealing process to separate the implantation region from a remainder region of the first semiconductor substrate. The method also includes forming a back-side interconnect structure over a back side of the transistor structure.

Abstract: A method for controlling carbide network in a bearing steel wire rod by controlling cooling and rolling, comprises the following steps: rapidly rolling a bar to a wire rod and spinning it into a loose coil, controlling the rolling temperature at 780° C.-880° C.; and the spinning temperature at 750° C.-850° C.; carrying out on-line controlling cooling of continuous loose coils using EDC water bath austempering cooling process, controlling the cooling rate at 2.0° C./s-10° C./s, and controlling the final cooling temperature within 620-630° C.; after EDC water bath austempering cooling, using slow cooling under a cover, and the temperature is controlled to be 400° C.-500° C. when being removed out of the cover; after slow cooling, collecting coils, and cooling in air to the room temperature.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: An adjustable leakage inductance transformer includes a magnetic core, a primary side coil and a secondary side coil. The magnetic core includes a magnetic core column structure, which has a central column, a first outer column and a second outer column. The primary side coil is wound on the first outer column and the second outer column by a first primary side coil loop number and a second primary side coil loop number, respectively. The secondary side coil is wound on the first outer column and the second outer column by a first secondary side coil loop number and a second secondary side coil loop number, respectively, the first primary side coil loop number is not equal to the first secondary side coil loop number, and the second primary side coil loop number is not equal to the second secondary side coil loop number.

Abstract: A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region forms a semiconductor fin.

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

Abstract: A semiconductor device includes a substrate; a first thermoelectric conduction leg, disposed on the substrate, and doped with a first type of dopant; a second thermoelectric conduction leg, disposed on the substrate, and doped with a second type of dopant, wherein the first and second thermoelectric conduction legs are spatially spaced from each other but disposed along a common row on the substrate; and a first intermediate thermoelectric conduction structure, disposed on a first end of the second thermoelectric conduction leg, and doped with the first type of dopant.

Abstract: A touch panel includes a substrate, touch signal lines, sub-pixels, touch electrode groups, and at least one common signal array. The touch signal lines and the sub-pixels are located on substrate. Each of the sub-pixels includes a switch element and a pixel electrode. The switch element is electrically connected to a corresponding scan line and a corresponding data line. The touch electrode groups include touch electrodes. The touch electrodes overlap the pixel electrodes of the sub-pixels. Each of the touch electrode groups is electrically connected to a corresponding one of the touch signal lines. The common signal array includes common electrodes. Each of the common electrodes overlaps at least one of the scan line and the data line. The number of the sub-pixels overlapped by the common signal array is greater than the number of the sub-pixels overlapped by each of the touch electrode groups.

Abstract: A system and method for image-guided microscopic illumination are provided. A processing module controls an imaging assembly such that a camera acquires an image or images of a sample in multiple fields of view, and the image or images are automatically transmitted to a processing module and processed by the first processing module automatically in real-time based on a predefined criterion so as to determine coordinate information of an interested region in each field of view. The processing module also controls an illuminating assembly to illuminate the interested region of the sample according to the received coordinate information regarding to the interested region, with the illumination patterns changing among the fields of view.

Abstract: Disclosed herein is a fuel for use in a combustor of a gas turbine, wherein the fuel is a gas mixture that comprises hydrogen and exhaust gas from a total combustor.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A product positioning method includes: collecting a product picture; performing integral image calculation on the product picture; and acquiring, according to the calculated integral image, coordinates of each vertex in the product picture by means of differential calculation. According to the present application, an integral image algorithm is applied to product positioning, such that when the product picture quality is not high, for example, the picture is blurry, and it is thus not convenient to position a product by using a picture edge algorithm or a template matching algorithm, the product picture and a background region can be quickly divided by using the integral image algorithm, thereby positioning the product and not being limited by poor picture quality.

Abstract: The present invention relates to processes for the preparation of biofuel from biomass by fast hydropyrolysis or fast pyrolysis, using hydrogen generated by sorption enhanced steam reforming. The present invention also relates to fixed bed tandem catalytic-upgrading processes, and reactors and hydrodeoxygenation (HDO) catalysts useful in those processes.

Abstract: A microscope-based system and a method for image-guided microscopic illumination are provided. The microscope-based system for image-guided microscopic illumination comprises a microscope, an illuminating assembly, an imaging assembly, a first processing module, and a second processing module. The microscope comprises a stage, and the stage is configured to be loaded with a sample. The imaging assembly comprises a camera. The processing modules are coupled to the microscope, the imaging assembly, and the illuminating assembly.

Abstract: A semiconductor device and method of making same are disclosed. In some embodiments, a method includes: forming a first thermoelectric conduction leg on a substrate; forming a second thermoelectric conduction leg on the substrate to be aligned with the first thermoelectric conduction leg along a same row; forming at least one intermediate thermoelectric conduction structure on an end of the second thermoelectric conduction leg; forming a contact structure to couple the first and second thermoelectric conduction legs via the at least one intermediate thermoelectric conduction structure; and recessing the substrate to form at least one trench substantially adjacent to a respective side edge of either the first thermoelectric conduction leg or the second thermoelectric conduction leg.