Patents by Inventor De Wang

De Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND FORMING METHOD THEREOF
    Publication number: 20180205013
    Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.
    Type: Application
    Filed: February 24, 2017
    Publication date: July 19, 2018
    Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen
  • Memory cell and manufacturing method thereof
    Patent number: 10020385
    Abstract: The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: July 10, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Shan Chiu, Shen-De Wang, Zhen Chen, Yuan-Hsiang Chang, Chih-Chien Chang, Jianjun Yang, Wei Ta
  • Implant isolated devices and method for forming the same
    Patent number: 10008532
    Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Wen-De Wang, Wen-I Hsu
  • SEAL RING STRUCTURES AND METHODS OF FORMING SAME
    Publication number: 20180175012
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first IC die and a second IC die. The first IC die includes a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.
    Type: Application
    Filed: August 1, 2017
    Publication date: June 21, 2018
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Wen-De Wang, Yung-Lung Lin
  • Flash memory cell
    Patent number: 9978758
    Abstract: A flash memory includes a substrate, a memory gate on the substrate, a charge-storage layer between the memory gate and the substrate, a select gate adjacent to the memory gate, a select gate dielectric layer between the select gate and the substrate, a first oxide-nitride spacer between the memory gate and the select gate, and a second oxide-nitride spacer. The select gate includes an upper portion and a lower portion. The second oxide-nitride spacer is disposed between the first oxide-nitride spacer and the upper portion of the select gate.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta, Chuan Sun
  • Semiconductor device and method of fabricating semiconductor device
    Patent number: 9978762
    Abstract: A method of fabricating a semiconductor device includes providing a substrate with a memory region and a logic region, forming a recess of the substrate in the memory region, forming a non-volatile gate stack in the recess, and forming a logic gate stack in the logic region after forming the non-volatile gate stack.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 22, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Ko-Chi Chen, Shen-De Wang
  • Semiconductor structure and manufacturing method thereof
    Patent number: 9966383
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
  • METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180108744
    Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.
    Type: Application
    Filed: December 5, 2017
    Publication date: April 19, 2018
    Inventors: WEICHANG LIU, ZHEN CHEN, SHEN-DE WANG, WANG XIANG, WEI TA
  • Vertically Integrated Image Sensor Chips and Methods for Forming the Same
    Publication number: 20180108703
    Abstract: A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Jeng-Shyan Lin, Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Wen-De Wang, Tzu-Hsuan Hsu
  • SEMICONDUCTOR DEVICE HAVING MEMORY CELL STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180108837
    Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.
    Type: Application
    Filed: November 23, 2016
    Publication date: April 19, 2018
    Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
  • Deep trench isolation structure in image sensor device
    Patent number: 9935147
    Abstract: An image sensor device includes a substrate having a front surface and a back surface, and a deep trench disposed at the front surface of the substrate. The deep trench has sidewalls, a bottom and an opening. A dielectric layer is disposed along the sidewalls and the bottom of the deep trench. An epitaxial layer is disposed on the front surface of the substrate. The deep trench and the epitaxial layer collectively define an air chamber. The deep trench has a chamfered portion at an interface between the epitaxial layer and the front surface of the substrate. The chamfered portion is free of dielectric layer.
    Type: Grant
    Filed: November 19, 2016
    Date of Patent: April 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Alexander Kalnitsky, Wen-De Wang
  • SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20180053756
    Abstract: A semiconductor device structure includes a first chip including a plurality of dielectric layers and a multi-layered metal structure embedded in the plurality of dielectric layer, a second chip bonded to the first chip to generate a bonding interface and including a metal structure, a first via structure extending through the first chip and crossing the bonding interface into the metal structure in the second chip, and a second via structure extending in the first chip and electrically connected to the multi-layered metal structure in the first chip. The first via structure further includes a first via metal and a first via dielectric layer, the first via dielectric layer interposes between the first via metal and the plurality of dielectric layers of the first chip and extends from the first chip to the metal structure in the second chip.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 22, 2018
    Inventors: CHENG-YING HO, WEN-DE WANG, JEN-CHENG LIU, DUN-NIAN YAUNG
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20180047842
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 15, 2018
    Inventors: Liang Yi, Shen-De Wang
  • 3DIC Seal Ring Structure and Methods of Forming Same
    Publication number: 20180033817
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Application
    Filed: October 11, 2017
    Publication date: February 1, 2018
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180033961
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a bottom metal layer, a resistive random access memory (ReRAM) cell structure, and an upper metal layer. The bottom metal layer is located above the substrate. The ReRAM cell structure is formed on the bottom metal layer. The ReRAM cell structure includes a bottom electrode, a memory cell layer, a top electrode, and a spacer. The memory cell layer is formed on the bottom electrode. The top electrode is formed on the memory cell layer. The spacer is formed on two sides of the bottom electrode, the memory cell layer and the top electrode. The upper metal layer is electrically connected to and directly contacting the top electrode.
    Type: Application
    Filed: September 9, 2016
    Publication date: February 1, 2018
    Inventors: Liang Yi, Chia-Ching Hsu, Shen-De Wang, Ko-Chi Chen
  • IMAGE SENSOR DEVICE AND METHOD OF FORMING SAME
    Publication number: 20180026069
    Abstract: An image sensor device includes a first substrate, an interconnect structure, a conductive layer, a conductive via and a second substrate. The first substrate includes a first region including a pixel array and a second region including a circuit. The interconnect structure is over the pixel array or the circuit. The interconnect structure electrically connecting the circuit to the pixel array. The conductive layer is on the interconnect structure. The conductive via passes through the second substrate and at least partially embedded in the conductive layer. The second substrate is over the conductive layer.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 25, 2018
    Inventors: Wen-De Wang, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Jeng-Shyan Lin
  • Semiconductor memory cell, semiconductor memory device, and method of manufacturing semiconductor memory device
    Patent number: 9865693
    Abstract: A semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge. Additionally, a method of manufacturing the semiconductor memory device is also provided.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: January 9, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Wei Ta
  • Semiconductor device having memory cell structure
    Patent number: 9859335
    Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Liang Yi, Shen-De Wang, Ko-Chi Chen
  • Vertically integrated image sensor chips and methods for forming the same
    Patent number: 9847368
    Abstract: A method includes bonding a Backside Illumination (BSI) image sensor chip to a device chip, forming a first via in the BSI image sensor chip to connect to a first integrated circuit device in the BSI image sensor chip, forming a second via penetrating through the BSI image sensor chip to connect to a second integrated circuit device in the device chip, and forming a metal pad to connect the first via to the second via.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Feng-Chi Hung, Dun-Nian Yaung, Jen-Cheng Liu, Szu-Ying Chen, Wen-De Wang, Tzu-Hsuan Hsu
  • Semicondcutor structure and semiconductor manufacturing process thereof
    Patent number: 9837366
    Abstract: A semiconductor structure has a semiconductor device, a first seal ring, and a second seal ring. The semiconductor device has a first surface and a second surface opposite to the first surface. The first seal ring is disposed on the first surface of the semiconductor device and adjacent to edges of the first surface. The second seal ring is disposed on the second surface of the semiconductor device and adjacent to edges of the second surface. A semiconductor manufacturing process is also provided.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hsun Liu, Chin-Yu Ku, Rung-De Wang, Wei-Lun Hsieh, Chia-Hua Wang, Jheng-Hong Chen, Pei-Shing Tsai