Patents by Inventor De Wang

De Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flash cell and forming process thereof
    Patent number: 9666680
    Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: May 30, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Hsiang Chang, Shen-De Wang, Chih-Chien Chang, Jianjun Yang, Aaron Chen
  • Flash memory and method of manufacturing the same
    Patent number: 9660106
    Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Weichang Liu, Zhen Chen, Shen-De Wang, Wei Ta, Yi-Shan Chiu, Yuan-Hsiang Chang
  • Semiconductor device and method of fabricating semiconductor device
    Patent number: 9659948
    Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: May 23, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Ko-Chi Chen, Shen-De Wang
  • FLASH CELL AND FORMING PROCESS THEREOF
    Publication number: 20170141200
    Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 18, 2017
    Inventors: Yuan-Hsiang Chang, Shen-De Wang, Chih-Chien Chang, JIANJUN YANG, Aaron Chen
  • Pad structure exposed in an opening through multiple dielectric layers in BSI image sensor chips
    Patent number: 9653508
    Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Shuang-Ji Tsai, Yueh-Chiou Lin
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20170117372
    Abstract: The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.
    Type: Application
    Filed: October 26, 2015
    Publication date: April 27, 2017
    Inventors: DONGDONG LI, Ko-Chi Chen, Shen-De Wang
  • SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170110469
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.
    Type: Application
    Filed: November 24, 2015
    Publication date: April 20, 2017
    Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
  • Backside structure and methods for BSI image sensors
    Patent number: 9613996
    Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
    Publication number: 20170084622
    Abstract: A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Chia-Ching Hsu, Ko-Chi Chen, Shen-De Wang
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20170077110
    Abstract: Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure.
    Type: Application
    Filed: October 27, 2015
    Publication date: March 16, 2017
    Inventors: Wei-Chang Liu, Zhen Chen, Shen-De Wang, Wang Xiang, Yi-Shan Chiu, Wei Ta
  • Semiconductor device with embedded cell and method of manufacturing the same
    Patent number: 9595588
    Abstract: A semiconductor device with embedded cell is provided. A silicon substrate has a first area with at least one first cell and a second area with at least one second cell. The first cell is positioned in the first area and formed in a trench of the silicon substrate, and the second cell is positioned in the second area and formed on the silicon substrate. The first cell includes a first dielectric layer formed on sidewalls and a bottom of the trench, a floating gate formed on the first dielectric layer and embedded in the trench, a second dielectric layer formed on the floating gate and embedded in the trench, and a control gate formed on the second dielectric layer and embedded in the trench, wherein the control gate is separated from the floating gate by the second dielectric layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: March 14, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Sung Huang, Ko-Chi Chen, Shen-De Wang
  • DEEP TRENCH ISOLATION STRUCTURE IN IMAGE SENSOR DEVICE
    Publication number: 20170069670
    Abstract: An image sensor device includes a substrate having a front surface and a back surface, and a deep trench disposed at the front surface of the substrate. The deep trench has sidewalls, a bottom and an opening. A dielectric layer is disposed along the sidewalls and the bottom of the deep trench. An epitaxial layer is disposed on the front surface of the substrate. The deep trench and the epitaxial layer collectively define an air chamber. The deep trench has a chamfered portion at an interface between the epitaxial layer and the front surface of the substrate. The chamfered portion is free of dielectric layer.
    Type: Application
    Filed: November 19, 2016
    Publication date: March 9, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hung CHEN, Dun-Nian YAUNG, Jen-Cheng LIU, Alexander KALNITSKY, Wen-De WANG
  • Non-volatile memory and fabricating method thereof
    Patent number: 9589977
    Abstract: The invention provides a non-volatile memory and a fabricating method thereof. The non-volatile memory includes a substrate, an embedded-type charge storage transistor, and a selection transistor. The substrate has an opening. The embedded-type charge storage transistor is disposed in the substrate. The embedded-type charge storage transistor includes a charge storage structure and a conductive layer. The charge storage structure is disposed on the substrate in the opening. The conductive layer is disposed on the charge storage structure and fills the opening. The selection transistor is disposed on the substrate at one side of the embedded-type charge storage transistor, wherein the selection transistor includes a metal gate structure. The non-volatile memory has excellent charge storage capacity.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: March 7, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Ko-Chi Chen, Shen-De Wang
  • Backside structure and methods for BSI image sensors
    Patent number: 9576999
    Abstract: BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • Back side illuminated image sensor having isolated bonding pads
    Patent number: 9570497
    Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuang-Ji Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Hsiao-Hui Tseng
  • Ridge structure for back side illuminated image sensor
    Patent number: 9570503
    Abstract: Provided is an image sensor device. The image sensor device includes a substrate having a front side and a back side. The image sensor includes first and second radiation-detection devices that are disposed in the substrate. The first and second radiation-detection devices are operable to detect radiation waves that enter the substrate through the back side. The image sensor also includes an anti-reflective coating (ARC) layer. The ARC layer is disposed over the back side of the substrate. The ARC layer has first and second ridges that are disposed over the first and second radiation-detection devices, respectively. The first and second ridges each have a first refractive index value. The first and second ridges are separated by a substance having a second refractive index value that is less than the first refractive index value.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Keng-Yu Chou, Pao-Tung Chen, Wen-De Wang
  • Method of fabricating deep trench isolation structure in image sensor and device thereof
    Patent number: 9520433
    Abstract: A method includes forming a deep trench isolation structure on a substrate, the substrate having a back surface opposite to a front surface, the deep trench isolation structure opening toward the front surface. An oxide layer is formed on the front surface of the substrate and sidewalls and bottom of the deep trench isolation structure. The oxide layer on the front surface of the substrate is removed. A portion of the substrate at the opening of the deep trench isolation structure is removed and an epitaxial layer is formed on the substrate.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: December 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Hung Chen, Dun-Nian Yaung, Jen-Cheng Liu, Alexander Kalnitsky, Wen-De Wang
  • Non-volatile memory structure and manufacturing method thereof
    Patent number: 9508835
    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 29, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Chung Chang, Shen-De Wang, Ya-Huei Huang, Feng-Ji Tsai, Chien-Hung Chen
  • Backside Structure and Methods for BSI Image Sensors
    Publication number: 20160336367
    Abstract: A back side image sensor and method of manufacture are provided. In an embodiment a bottom anti-reflective coating is formed over a substrate, and a metal shield layer is formed over the bottom anti-reflective coating. The metal shield layer is patterned to form a grid pattern over a sensor array region of the substrate, and a first dielectric layer and a second dielectric layer are formed to at least partially fill in openings within the grid pattern.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Inventors: Chun-Chieh Chuang, Dun-Nian Yaung, Jen-Cheng Liu, Wen-De Wang, Keng-Yu Chou, Shuang-Ji Tsai, Min-Feng Kao
  • Flash cell and forming process thereof
    Patent number: 9455322
    Abstract: A flash cell forming process includes the following steps. A first gate is formed on a substrate. A first spacer is formed at a side of the first gate, where the first spacer includes a bottom part and a top part. The bottom part is removed, thereby an undercut being formed. A first selective gate is formed beside the first spacer and fills into the undercut. The present invention also provides a flash cell formed by said flash cell forming process. The flash cell includes a first gate, a first spacer and a first selective gate. The first gate is disposed on a substrate. The first spacer is disposed at a side of the first gate, where the first spacer has an undercut at a bottom part, and therefore exposes the substrate. The first selective gate is disposed beside the first spacer and extends into the undercut.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Shan Chiu, Shen-De Wang, Weichang Liu, Wei Ta, Zhen Chen, Wang Xiang