Abstract: A method based on standalone secondary synchronization signals (SSSs) can include receiving a configuration of an SSS burst at a user equipment (UE) from a base station in a wireless communication network. The SSS burst can include standalone SSSs grouped into SSS sets. Each SSS set can be associated with a beam index. The configuration can indicate frequency and timing locations of the standalone SSSs. The method can further include performing pre-synchronization, radio resource management (RRM) measurement, or cell detection based on the standalone SSSs in the SSS burst.

Abstract: Aspects of the disclosure further provide various apparatuses and methods for wireless communications. One apparatus includes processing circuitry that when a first uplink transmission on a source cell and a second uplink transmission on a target cell overlap in a frequency domain, determines whether the first uplink transmission on the source cell and the second uplink transmission on the target cell are in overlapping time resources. When the first uplink transmission on the source cell and the second uplink transmission on the target cell are in the overlapping time resources, the processing circuitry cancels the first uplink transmission on the source cell and performs the second uplink transmission on the target cell.

Abstract: A micro light-emitting diode is provided. The micro light-emitting diode includes a first-type semiconductor layer having a first doping type; a light-emitting layer over the first-type semiconductor layer; a first-type electrode over the first-type semiconductor layer; a second-type semiconductor layer having a second doping type over the light-emitting layer, wherein the second doping type is different from the first doping type; a second-type electrode over the second-type semiconductor layer; and a barrier layer under the first-type semiconductor layer and away from the first-type electrode and the second-type electrode, wherein the barrier layer includes a doped region having the second doping type.

Abstract: A micro light-emitting device, including a first type semiconductor layer, a light-emitting layer, a second type semiconductor layer, a first type electrode, a second type electrode, and a light reflection layer, is provided. The light-emitting layer is arranged on the first type semiconductor layer. The second type semiconductor layer is arranged on the light-emitting layer. The first type electrode and the second type electrode are both arranged on the second type semiconductor layer. The light reflection layer is arranged between the light-emitting layer and the first type electrode. The light reflection layer includes an oxidized area and a non-oxidized area. A reflectance of the oxidized area is greater than a reflectance of the non-oxidized area. An orthographic projection of a part of the oxidized area on the first type semiconductor layer and an orthographic projection of the first type electrode on the first type semiconductor layer at least partially overlap.

Abstract: A micro semiconductor device, including a semiconductor structure, a current confinement layer, a first type electrode, and a second type electrode, is provided. The current confinement layer is disposed in the semiconductor structure. The current confinement layer includes an oxidized area and a non-oxidized area. The first type electrode and the second type electrode are both disposed on the current confinement layer. An orthographic projection of a part of the oxidized area on a bottom surface of the semiconductor structure away from the first type electrode and the second type electrode is located between an orthographic projection of the first type electrode on the bottom surface and an orthographic projection of the second type electrode on the bottom surface.

Abstract: Aspects of the disclosure provide an electronic device including processing circuitry and a method for beam management (BM) with power saving. The processing circuitry can receive a reference signal from a network via a serving beam pair used for downlink (DL) transmission between the network and an electronic device. The serving beam pair can include a serving transmission (Tx) beam transmitted from the network and a serving reception (Rx) beam received by the electronic device. The processing circuitry can determine a signal quality of the reference signal. When the signal quality is determined to satisfy a power saving condition, the processing circuitry can reduce beam measurements in the BM for beam pairs including Tx beams transmitted from the network and respective Rx beams received by the electronic device. The beam pairs can include the serving beam pair and one or more candidate beam pairs.

Abstract: Board member fastener used to rivet first board member and second board member. First and second board members each have drilled therein a different diameter of hole. First board member provides first through hole. Second board member provides second through hole. Top of first through hole of first board member is formed with stop surface that tapers toward outer diameter so that when board member fastener is punch impacted, board member fastener sinks into interior of first through hole to cut second board member and to deform, and first board member is forced by sinking stress of board member fastener and tightly pressed on second board member upon punch impact, and thus, board member fastener, first board member and second board member are deformed and fitted to each other, achieving a riveting structure that can be applied to different materials and can overcome deformation caused by heat expansion and contraction.

Abstract: A UE receives one or more modulation symbols on one or more resource elements prior to an ON duration in a particular DRX cycle in RRC connected mode. The one or more resource elements are allocated to carry a wake-up signal. The UE performs a blind detection of the wake-up signal on the one or more modulation symbols in accordance with a DCI format and a group identifier identifying a group of UEs including the UE. The wake-up signal includes an indication that indicates whether one or more UEs of the group of UEs should monitor a down link control channel in the ON duration. The UE determines whether to operate in a normal state and monitor a down link control channel in the ON duration based on the wake-up signal when the wake-up signal is detected.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region adjacent to the gate structure. A top of the dielectric cap is oxidized. After oxidizing the top of the dielectric cap, an etch stop layer is deposited over the dielectric cap and an interlayer dielectric (ILD) layer over the etch stop layer. The ILD layer and the etch stop layer are etched to form a via opening extending though the ILD layer and the etch stop layer. A source/drain via is filled in the via opening.

Abstract: Methods are proposed for UE to perform radio link monitoring (RLM) and beam failure detection (BFD) measurements in a relaxed measurement state with an extended evaluation period for power saving. Different criteria for UE to enter and exit the relaxed RLM/BFD measurement state are proposed. In relaxed measurement state, UE can perform RLM/BFD measurements with an extended evaluation period by a scaling factor K when the serving cell quality is higher than a threshold and/or when the serving cell quality variation is lower than a threshold within a time period.

Abstract: A method comprises forming a gate dielectric cap over a gate structure; forming source/drain contacts over the semiconductor substrate, with the gate dielectric cap laterally between the source/drain contacts; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the etch-resistant layer and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a via opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the via opening such that one of the source/drain contacts is exposed, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and depositing a metal material to fill the deepened via opening.

Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending though the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.

Abstract: A method comprises forming a gate structure between gate spacers; etching back the gate structure to fall below top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structure; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an ILD layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the doped region of the gate dielectric cap; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: A method includes depositing a dielectric cap over a gate structure. A source/drain contact is formed over a source/drain region after forming the dielectric cap. A top of the dielectric cap is doped to form a doped region in the dielectric cap. After doping the top of the dielectric cap, a etch stop layer and an interlayer dielectric (ILD) layer are deposited over the dielectric cap. A via opening is formed to extend though the ILD layer and the etch stop layer to expose the source/drain contact. A source/drain via is filled in the via opening.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; etching back the gate structure; forming a gate dielectric cap over the etched back gate structure; depositing an etch-resistant layer over the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an interlayer dielectric (ILD) layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the etch-resistant layer; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the etch-resistant layer at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.

Abstract: A circuit build-up film for wafer-level packaging (WLP) includes 40 to 60 parts by mass of a first epoxy resin, 15 to 30 parts by mass of a second epoxy resin, 25 to 50 parts by mass of a curing agent, 0.1 to 5 parts by mass of a curing accelerator, 5 to 20 parts by mass of an additive, 320 to 650 parts by mass of an inorganic filler, and 0.01 to 5 parts by mass of a silane coupling agent (SCA), where the additive is obtained by subjecting an epoxy resin to a reaction with a polyhydroxyl-terminated dendritic crosslinking agent. The build-up film shows prominent fluidity during heating and curing, and can completely fill gaps among wafers. A packaging process using the build-up film is simple. Regardless of the number of wafers, packaging can be completed through one procedure with the build-up film.

Abstract: Aspects of the disclosure further provide various apparatuses and methods for wireless communications. One apparatus includes processing circuitry that can determine a first transmission power for a first uplink transmission associated with the source cell and a second transmission power for a second uplink transmission associated with the target cell. When the first uplink transmission and the second uplink transmission overlap in time domain and a total power of the first transmission power and the second transmission power is above a first threshold, the processing circuitry reduces the first transmission power for the first uplink transmission to a third transmission power so that a total power of the second transmission power and the third transmission power is equal to or less than the first threshold. The processing circuitry performs the first uplink transmission at the third transmission power and the second uplink transmission at the second transmission power.

Abstract: A wafer carrier including a rotation axis, a center flat region, a wafer distributing region and a plurality of wafer accommodating grooves is provided. The rotation axis passes through a center of the center flat region and a surface of the center flat region is a flat surface. The wafer distributing region surrounds the center flat region. The plurality of wafer accommodating grooves are disposed in the wafer distributing region and arranged in a single virtual loop. A diameter of each of the wafer accommodating grooves is D, and a radius of the center flat region is larger than 0.5D. A wafer carrier and a metal organic chemical vapor deposition apparatus using any of the above two wafer carriers are further provided.

Abstract: Aspects of the disclosure provide a method and an apparatus for monitoring a paging occasion (PO). For example, the apparatus can include receiving circuitry and processing circuitry. The receiving circuitry can be configured to receive an SS block burst set including a sequence of SS blocks that are each associated with a paging early indicator indicating whether a paging massage is presented in at least one PO that comes later than the SS block burst set. The processing circuitry can be configured to monitor the at least one PO for the paging message when the paging early indicator indicates that the paging message is presented in the at least one PO, and enter a sleep state without monitoring the at least one PO when the paging early indicator indicates that the paging message is not presented in the at least one PO.