Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

Abstract: A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices for error handling of data received across a multi-Lane Link compliant with a Peripheral Component Interconnect Express (PCIe) protocol. The system can include an upstream device to transmit a data packet across a multi-Lane Link compliant with the PCIe protocol and a downstream device connected to the upstream device across a multi-Lane Link, the downstream device comprising a receiver that comprises a deframer logic. The deframer logic can identify a Framing error in a received data packet received on one Link of the multi-Lane Link; determine that one or more other data packets received on one or more other Links of the multi-Lane Link do not present a Framing error; and process the received data packet based on the one or more other data packets received on the one or more other Links.

Abstract: Aspects of the embodiments are directed to systems, methods, and devices that can activate forward error correction (FEC) based on the channel loss of a channel. The channel's loss can be characterized as a high loss channel if the channel loss exceeds a predetermined threshold value. For channels with high loss and for those that operate at high data rates (e.g., data rates commensurate with PCIe Gen 4 or Gen 5), FEC can be activated so that the channels can achieve higher data rates.

Abstract: Data is accessed from a particular register first device that is connected to a second device via a link that includes at least one retimer device. The particular register corresponds to requests to be sent in in-band transactions with the retimer, and the data corresponds to a particular transaction with the retimer. At least one ordered set is generated at the first device to comprise a subset of bits encoded with the data, where the ordered set with the encoded subset of bits is to be sent on the link and the subset of bits are to be processed by the retimer in the particular transaction.

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

Abstract: A retimer device receives a first signal from a first device and regenerates the first signal to send to a second device. The retimer further receive a second signal from the second device and regenerates the second signal to send to the first device, where the first device includes a processor device. The retimer includes a sideband interface to connect to the first device and further includes protocol logic to monitor the first signal, determine that the first signal includes a pattern defined in a protocol to identify a protocol activity, and participate in performance of the protocol activity using the sideband interface.

Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.

Abstract: An apparatus for pooling memory resources across multiple nodes is described herein. The apparatus includes a shared memory controller, wherein each node of the multiple nodes is connected to the shared memory controller. The apparatus also includes a pool of memory connected to the shared memory controller, wherein a portion of the pool of memory is allocated to each node of the multiple nodes.

Abstract: A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: Data is sent to correspond to a load/store-type operation associated with shared memory over a link according to a memory access link protocol and the memory access link protocol is to be overlaid on another, different link protocol. A request is sent to enter a low power state, where the request is to include a data value encoded in a field of a token, the token is to indicate a start of packet data and is to further indicate whether subsequent data to be sent after the token is to include data according to one of the other link protocol and the memory access link protocol.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line.

Abstract: Virtual machine (VM) migration in rack scale systems is disclosed. A source shared memory controller (SMC) of implementations includes a direct memory access (DMA) move engine to establish a first virtual channel (VC) over a link with a destination SMC, the destination SMC coupled to a destination node hosting a VM that is migrated to the destination node from a source node coupled to the source SMC, and transmit, via the first VC to the destination SMC, units of data corresponding to the VM and directory state metadata associated with each unit of data. The source SMC includes a demand request component to establish a second VC over the link, receive, via the second VC from the destination SMC, a demand request for one of the units of data corresponding to the VM, and transmit, via the second VC, the requested unit of data and corresponding directory state metadata.

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

Abstract: A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.