Patents by Inventor Debendra Das Sharma

Debendra Das Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for dynamically allocating storage resources to compute nodes
    Patent number: 9823849
    Abstract: Provided are a method, system, computer readable storage medium, and switch for configuring a switch to assign partitions in storage devices to compute nodes. A management controller configures the switch to dynamically allocate partitions of at least one of the storage devices to the compute nodes based on a workload at the compute node.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: November 21, 2017
    Assignee: INTEL CORPORATION
    Inventors: Mark A. Schmisseur, Mohan J. Kumar, Balint Fleischer, Debendra Das Sharma, Raj K. Ramanujan
  • Physical interface for a serial interconnect
    Patent number: 9779053
    Abstract: An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function as a drift buffer or an elastic buffer by a voltage level on a buffer control line. The physical interface also includes encoding logic that can be enabled or disabled by a voltage level on a logic control line. Further, the physical interface also includes and an ordered set generator that can be enabled or disabled by a voltage level on a communications control line.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 3, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich, Venkatraman Iyer, Michelle C. Jen, Rahul R. Shah, Eric M. Lee
  • IN-BAND RETIMER REGISTER ACCESS
    Publication number: 20170270062
    Abstract: Data is accessed from a particular register first device that is connected to a second device via a link that includes at least one retimer device. The particular register corresponds to requests to be sent in in-band transactions with the retimer, and the data corresponds to a particular transaction with the retimer. At least one ordered set is generated at the first device to comprise a subset of bits encoded with the data, where the ordered set with the encoded subset of bits is to be sent on the link and the subset of bits are to be processed by the retimer in the particular transaction.
    Type: Application
    Filed: June 30, 2016
    Publication date: September 21, 2017
    Inventor: Debendra Das Sharma
  • SERIAL SIDEBAND SIGNALING LINK
    Publication number: 20170235701
    Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques include an apparatus for sideband signaling including a first serial sideband link module and a second serial sideband link module. The first serial sideband link module is to propagate packets from an upstream port to a downstream port via a first signaling lane, and the second serial sideband link module is to propagate packets from the downstream port to the upstream port via a second signaling lane.
    Type: Application
    Filed: December 24, 2014
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventors: Akshay Pethe, Mahesh Wagh, David Harriman, Su Wei Lim, Debendra Das Sharma, Daniel Froelich, Venkatraman Iyer, James Jaussi, Zuoguo Wu
  • Shared buffered memory routing
    Patent number: 9720838
    Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Michelle C. Jen, Brian S. Morris
  • Redriver link testing
    Patent number: 9692589
    Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Fulvio Spagna, Debendra Das Sharma
  • ARCHITECTURE FOR SOFTWARE DEFINED INTERCONNECT SWITCH
    Publication number: 20170177528
    Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: David J. Harriman, Manjari Kulkarni, Akshay G. Pethe, Sean O. Stalley, Mahesh Wagh, Debendra Das Sharma
  • PCI EXPRESS ENHANCEMENTS
    Publication number: 20170163286
    Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.
    Type: Application
    Filed: December 26, 2013
    Publication date: June 8, 2017
    Inventors: Zuoguo WU, Debendra DAS SHARMA, Md. Mohiuddin MAZUMDER, Subas BASTOLA, Kai XIAO
  • Low-latency internode communication
    Patent number: 9665415
    Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.
    Type: Grant
    Filed: September 26, 2015
    Date of Patent: May 30, 2017
    Assignee: INTEL CORPORATION
    Inventors: Debendra Das Sharma, Michelle C. Jen, Joseph Murray
  • Apparatus, system, and method for improving equalization with a hardware driven algorithm
    Patent number: 9645965
    Abstract: A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Kanaka Lakshimi Siva Prasad Gadey Naga Venkata, Prahladachar Jayaprakash Bharadwaj
  • HIGH PERFORMANCE INTERCONNECT
    Publication number: 20170109315
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert H. Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • High performance interconnect
    Patent number: 9626321
    Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: April 18, 2017
    Assignee: Intel Corporation
    Inventors: Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue, Arvind A. Kumar, Debendra Das Sharma, Jeffrey C. Swanson, Bahaa Fahim, Vedaraman Geetha, Aaron T. Spink, Fulvio Spagna, Rahul R. Shah, Sitaraman V. Iyer, William Harry Nale, Abhishek Das, Simon P. Johnson, Yuvraj S. Dhillon, Yen-Cheng Liu, Raj K. Ramanujan, Robert A. Maddox, Herbert H. Hum, Ashish Gupta
  • LOW-LATENCY INTERNODE COMMUNICATION
    Publication number: 20170091003
    Abstract: A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI3) or electrical process logic (e.g., PCIe) on the “node side” between the nodes and a pooled memory controller (or pooled storage controller), and on the “pooled side” between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Debendra Das Sharma, Michelle C. Jen, Joseph Murray
  • MULTICHIP PACKAGE LINK
    Publication number: 20170083475
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Application
    Filed: December 26, 2013
    Publication date: March 23, 2017
    Applicant: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Assisted Coherent Shared Memory
    Publication number: 20170052860
    Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.
    Type: Application
    Filed: June 8, 2016
    Publication date: February 23, 2017
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • DATA COHERENCY MODEL AND PROTOCOL AT CLUSTER LEVEL
    Publication number: 20170046208
    Abstract: An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using a protocol that includes input/output (I/O) semantics and memory semantics. The apparatus also includes a reflected memory region. The reflected memory region is a portion of the global persistent memory, and each node of a plurality of nodes maps the reflected memory region into a space that is not cacheable. Further, the apparatus includes a semaphore memory. The semaphore memory provides a hardware assist for enforced data coherency.
    Type: Application
    Filed: June 9, 2016
    Publication date: February 16, 2017
    Inventors: Debendra Das Sharma, Mohan J. Kumar, Balint Fleischer
  • Test logic for a serial interconnect
    Patent number: 9552269
    Abstract: An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages, wherein each reporting message is associated with a link sub-segment in a link in the serial interconnect, and each reporting message comprises a status region for the associated link sub-segment to report transmission errors. The test logic also includes analysis logic to record errors in the link sub-segment.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Daniel S. Froelich
  • Probabilistic flit error checking
    Patent number: 9552253
    Abstract: A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic redundancy check (CRC) value of the flit. The link includes a plurality of lanes. It is determined that the one or more particular bits were sent over one or more particular lanes of the link. The bit error is associated with the one or more particular lanes based on determining that the affected bits were transmitted over the particular lanes.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Robert G. Blankenship, Debendra Das Sharma
  • REDRIVER LINK TESTING
    Publication number: 20170019247
    Abstract: A redriver is provided that includes a receiver to receive a signal from a first device that includes a portion of a defined binary sequence, a drift buffer to retime the binary sequence and provide a seed to a linear feedback shift register (LFSR) from the binary sequence, the LFSR to generate an expected version of the binary sequence from the seed, and pattern checking logic to compare a sequence in subsequent signals received from the first device with the expected version of the binary sequence generated by the LFSR.
    Type: Application
    Filed: September 26, 2015
    Publication date: January 19, 2017
    Inventors: Venkatraman Iyer, Fulvio Spagna, Debendra Das Sharma
  • SHARING MEMORY AND I/O SERVICES BETWEEN NODES
    Publication number: 20170004098
    Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.
    Type: Application
    Filed: December 26, 2013
    Publication date: January 5, 2017
    Applicant: Intel Corporation
    Inventors: Debendra Das Sharma, Robert G. Blankenship, Suresh S. Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen, Mohan J. Kumar, Brian S. Morris