Abstract: Technologies for providing local disaggregation of memory include a compute sled. The compute sled includes a compute engine having a processor. The compute engine receives a request to perform a memory access operation on data residing in a first memory (e.g., a storage class memory) of the compute sled. The compute engine determines whether the data is cached in a second memory (e.g., a dynamic random-access memory (DRAM)). The compute engine performs, in response to a determination that the data is not cached in the second memory via a transactional protocol over a serial link connecting the processor and the first memory, the requested memory access operation.

Abstract: The present disclosure describes a number of embodiments related to devices and techniques for implementing an interconnect switch to provide a switchable low-latency bypass between node resources such as CPUs and accelerator resources for caching. A resource manager may be used to receive an indication of a node of a plurality of nodes and an indication of an accelerator resource of a plurality of accelerator resources to connect to the node. If the indicated accelerator resource is connected to another node of the plurality of nodes, then transmit, to a interconnect switch, one or more hot-remove commands. The resource manager may then transmit to the interconnect switch one or more hot-add commands to connect the node resource and the accelerator resource.

Abstract: A port of a computing device includes multiple receiver-transmitter pairs, each of the receiver-transmitter pairs including a respective receiver and a respective transmitter. The device further includes state machine logic that detects a training sequence received by a particular one of the receiver-transmitter pairs on a particular lane from a tester device. The training sequence includes a value to indicate a test of the particular receiver-transmitter pair by the tester device. The particular receiver-transmitter pair enters a first link state in association with the test and one or more other receiver-transmitter pairs of the port enter a second link state different from the first link state in association with the test to cause crosstalk to be generated on the particular lane during the test.

Abstract: Aspects of the embodiments are directed to systems, methods, and computer program products that facilitate a downstream port to operate in Separate Reference Clocks with Independent Spread Spectrum Clocking (SSC) (SRIS) mode. The system can determine that the downstream port supports one or more SRIS selection mechanisms; determine a system clock configuration from the downstream port to a corresponding upstream port connected to the downstream port by the PCIe-compliant link; set an SRIS mode in the downstream port; and transmit data across the link from the downstream port using the determined system clock configuration.

Abstract: An apparatus is described. The apparatus includes a non volatile memory module for insertion into a rack implemented modular computer. The non volatile memory module includes a plurality of memory controllers. The non volatile memory includes respective non-volatile random access memory coupled to each of the memory controllers. The non volatile memory module includes a switch circuit to circuit switch incoming requests and outgoing responses between the rack's backplane and the plurality of memory controllers. The incoming requests are sent by one or more CPU modules of the rack implemented modular computer. The outgoing responses are sent to the one or more CPU modules.

Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

Abstract: An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

Abstract: Aspects of the embodiments are directed to systems and methods for performing link training using stored and retrieved equalization parameters obtained from a previous equalization procedure. As part of a link training sequence, links interconnecting an upstream port with a downstream port and with any intervening retimers, can undergo an equalization procedure. The equalization parameter values from each system component, including the upstream port, downstream port, and retimer(s) can be stored in a nonvolatile memory. During a subsequent link training process, the equalization parameter values stored in the nonvolatile memory can be written to registers associated with the upstream port, downstream port, and retimer(s) to be used to operate the interconnecting links. The equalization parameter values can be used instead of performing a new equalization procedure or can be used as a starting point to reduce latency associated with equalization procedures.

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

Abstract: A shared memory controller receives, from a computing node, a request associated with a memory transaction involving a particular line in a memory pool. The request includes a node address according to an address map of the computing node. An address translation structure is used to translate the first address into a corresponding second address according to a global address map for the memory pool, and the shared memory controller determines that a particular one of a plurality of shared memory controllers is associated with the second address in the global address map and causes the particular shared memory controller to handle the request.

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to provide multi-interconnect protocol communication. In an embodiment, an apparatus for providing multi-interconnect protocol communication may include a component comprising at least one connector operative to connect the component to at least one off-package device via a standard interconnect protocol, and logic, at least a portion of the logic comprised in hardware, the logic to determine data to be communicated via a multi-interconnect protocol, provide the data to a multi-protocol multiplexer to determine a route for the data, route the data on-package responsive to the multi-protocol multiplexer indicating a multi-interconnect on-package mode, and route the data off-package via the at least one connector responsive to the multi-protocol multiplexer indicating a multi-interconnect off-package mode. Other embodiments are described.

Abstract: Virtual machine (VM) migration in rack scale systems is disclosed. A source shared memory controller (SMC) of implementations includes a direct memory access (DMA) move engine to establish a first virtual channel (VC) over a link with a destination SMC, the destination SMC coupled to a destination node hosting a VM that is migrated to the destination node from a source node coupled to the source SMC, and transmit, via the first VC to the destination SMC, units of data corresponding to the VM and directory state metadata associated with each unit of data. The source SMC includes a demand request component to establish a second VC over the link, receive, via the second VC from the destination SMC, a demand request for one of the units of data corresponding to the VM, and transmit, via the second VC, the requested unit of data and corresponding directory state metadata.

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract: A port of a computing device is to communicate with another device over a link, the port including physical layer logic of a first protocol, link layer logic of each of a plurality of different protocols, and protocol negotiation logic to determine which of the plurality of different protocols to apply on the link. The protocol negotiation logic is to send and receive ordered sets in a configuration state of a link training state machine of the first protocol, where the ordered sets include an identifier of a particular one of the plurality of different protocols. The protocol negotiation logic is to determine from the ordered sets that a link layer of the particular protocol is to be applied on the link.

Abstract: A port of a computing device is to connect to another device over a link and use equalization logic to perform equalization of the link at a plurality of different data rates. The equalization logic may identify that the other device supports bypassing a sequential equalization mode, determine a maximum data rate supported by the devices on the link, and participate in equalization of the link at the maximum supported data rate before equalizing the link at one or more other data rates lower than the maximum supported data rate in the plurality of data rates.

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

Abstract: A retimer device is provided that includes an elasticity buffer, a receiver, and a controller. The elasticity buffer adds or subtracts data in the elasticity buffer to compensate for different bit rates of two devices to be connected over a link, where the retimer is positioned between the two devices on the link. The receiver receives a data stream to be sent between the two devices on the link. The controller determines, from the data stream, a modification to one or more characteristics of the link, and causes size of the elasticity buffer to be changed from a first size to a second size based on the modification.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: There is disclosed in an example an interconnect apparatus having: a root circuit; and a downstream circuit comprising at least one receiver; wherein the root circuit is operable to provide a margin test directive to the downstream circuit during a normal operating state; and the downstream circuit is operable to perform a margin test and provide a result report of the margin test to the root circuit. This may be performed in-band, for example in the L0 state. There is also disclosed a system comprising such an interconnect, and a method of performing margin testing.

Abstract: Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit, called a KTI (Keizer Technology Interface) Flit, is implemented in a coherent multi-layer protocol supporting coherent memory transactions. The KTI Flit has a basic format that supports use of configurable fields to implement KTI Flits with specific formats that may be used for corresponding transactions. In one aspect, the KTI Flit may be formatted as multiple slots used to support transfer of multiple respective pieces of transaction data in a single Flit. The KTI Flit can also be configured to support various types of transactions and multiple KTI Flits may be combined into packets to support transfer of data such as cache line transfers.