Abstract: A solar cell assembly includes a bendable substrate and multiple solar cells to be mounted over different surfaces of an electronic device. The bendable substrate includes an electrical contact to couple to an electrical contact on one of the surfaces of the electronic device. Thus, the electronic device only needs an electrical connection on one surface, and the solar cell assembly can mount solar cells on multiple surfaces to couple to the one electrical connection.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.

Abstract: Embodiments are directed to semiconductor packaging having reduced sized plated through hole (PTH) pads by eliminating the margin of the pad-to-PTH alignment and enabling finer traces on the core of the substrate.

Abstract: A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the mounting substrate die side. An electrically conductive first plug is in contact with the surface finish layer and an electrically conductive subsequent plug is disposed on the mounting substrate land side and it is electrically coupled to the electrically conductive first plug and disposed directly below the electrically conductive first plug.

Abstract: Devices and methods include an electronic package having a through-mold interconnect are shown herein. Examples of the electronic package include a package assembly. The package assembly including a substrate having a first substrate surface. The first substrate surface including a conductive layer attached to the first substrate surface. The package assembly includes a die communicatively coupled to the conductive layer and a contact block. The contact block including a first contact surface on one end of the contact block, a second contact surface on an opposing side of the contact block, and a contact block wall extended therebetween. The contact block includes a conductive material. The first contact surface is coupled to the package assembly with a joint extended partially up the contact block wall. The electronic package further includes an overmold covering portions of the substrate, conductive layer, and die. The second contact surface of the contact block is exposed through the overmold.

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.

Abstract: A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.

Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

Abstract: A photonic package includes a photonic device having a photon emitter on the front side of the die. A beam of photons from the photon emitter passing from the front side to the backside of the die, passes through the substrate material of the die which is substantially transparent to the beam of photons, to the backside of the die. Other embodiments are also described.

Abstract: 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.

Abstract: A flexible computing fabric and a method of forming thereof. The flexible computing fabric includes an electronic substrate including one or more channels and including at least two ends. At least one computational element is mounted on the electronic substrate between the two ends and at least one functional element is mounted on the electronic substrate between the two ends. The channels form an interconnect between the elements. In addition, the electronic substrate is flexible and exhibits a flexural modulus in the range of 0.1 GPa to 30 GPa.

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

Abstract: A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to the first substrate, and a heat spreader (140) adjacent to a second surface (111) of the die. The heat spreader makes contact with both the first substrate and the second substrate.

Abstract: Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.