Patents by Inventor Dechao Guo

Dechao Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED METAL GATE CMOS DEVICES
    Publication number: 20180090381
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 29, 2018
    Inventors: Ruqiang BAO, Dechao GUO, Vijay NARAYANAN
  • FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
    Publication number: 20180090599
    Abstract: Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.
    Type: Application
    Filed: July 18, 2017
    Publication date: March 29, 2018
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
    Publication number: 20180090604
    Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
    Type: Application
    Filed: December 30, 2016
    Publication date: March 29, 2018
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • FORMING A SACRIFICIAL LINER FOR DUAL CHANNEL DEVICES
    Publication number: 20180090606
    Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
    Type: Application
    Filed: June 21, 2017
    Publication date: March 29, 2018
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
    Publication number: 20180083120
    Abstract: Methods of forming a semiconductor device include laterally etching a dummy gate to recess the dummy gate underneath a spacer layer, such that the spacer layer overhangs the dummy gate. A sidewall of the dummy gate is nitridized. The dummy gate is etched away without removing the nitridized sidewall.
    Type: Application
    Filed: May 15, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
    Publication number: 20180083013
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
    Publication number: 20180083015
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: June 7, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
    Publication number: 20180083016
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: October 19, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT
    Publication number: 20180083017
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • SELF-ALIGNED SPACER FOR CUT-LAST TRANSISTOR FABRICATION
    Publication number: 20180082905
    Abstract: Semiconductor devices include one or more semiconductor fins. A gate is formed over the one or more semiconductor fins. A vertical sidewall is formed at a perimeter of the gate, the vertical sidewall having a uniform thickness along its height. A power rail is formed in contact with the vertical sidewall.
    Type: Application
    Filed: January 13, 2017
    Publication date: March 22, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Threshold voltage modulation through channel length adjustment
    Patent number: 9922983
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • Threshold voltage modulation through channel length adjustment
    Patent number: 9922984
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
  • SILICON NITRIDE FILL FOR PC GAP REGIONS TO INCREASE CELL DENSITY
    Publication number: 20180069002
    Abstract: A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.
    Type: Application
    Filed: November 7, 2017
    Publication date: March 8, 2018
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Integrated metal gate CMOS devices
    Patent number: 9899264
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • INTEGRATED METAL GATE CMOS DEVICES
    Publication number: 20180006033
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: April 28, 2017
    Publication date: January 4, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • INTEGRATED METAL GATE CMOS DEVICES
    Publication number: 20180005891
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Silicon nitride fill for PC gap regions to increase cell density
    Patent number: 9859275
    Abstract: A semiconductor device is provided comprising a substrate, two or more semiconductor fins, and one or more gates. A flowable oxide layer is deposited on the semiconductor device. An area between the two or more semiconductor fins is etched such that the substrate is exposed. An insulating layer is deposited within the etched area. At least the flowable oxide layer is removed.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices
    Patent number: 9859286
    Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • FORMATION OF A SEMICONDUCTOR DEVICE WITH SELECTIVE NITRIDE GROWN ON CONDUCTOR
    Publication number: 20170373063
    Abstract: A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of transistors. An oxide is deposited over the source and drain of the transistors. A block mask is placed over the first transistor, and the oxide is removed from the second transistor. The block mask is removed and an epitaxial growth is performed on the second transistor. A selective nitridation is performed on the second transistor, and the process is repeated for the first transistor. Other embodiments are also described.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Partial sacrificial dummy gate with CMOS device with high-k metal gate
    Patent number: 9853116
    Abstract: A gate structure in a semiconductor device includes: a gate stack formed on a substrate with three sections, a bottom portion, a top portion, and a sacrificial cap layer over the top portion; gate spacers, source and drain regions, a nitride encapsulation over top and sidewalls of the gate stack after removal of the sacrificial cap layer, an organic planarizing layer over the nitride encapsulation, planarizing the encapsulation, and silicidation performed over the source and drain regions and the bottom portion after removal of the nitride encapsulation, the organic planarizing layer, and the top portion of the gate stack.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Shu-jen Han, Daniel J. Jaeger, Yu Lu, Keith Kwong Hon Wong