Abstract: A method for fabricating a semiconductor device includes forming a first inner spacer layer along a substrate and a nanosheet stack disposed on the substrate, performing an ultraviolet (UV) condensation process to form a hardened inner spacer from the first inner spacer layer, forming a second inner spacer layer along the hardened inner spacer, and removing material to form inner spacers by performing an inner spacer etch.

Abstract: Techniques are provided to fabricate semiconductor devices having a nanosheet field-effect transistor device disposed on a semiconductor substrate. The nanosheet field-effect transistor device includes a nanosheet stack structure including a semiconductor channel layer and a source/drain region in contact with an end portion of the semiconductor channel layer of the nanosheet stack structure. A trench formed in the source/drain region is filled with a metal-based material. The metal-based material filling the trench in the source/drain region mitigates the effect of source/drain material overfill on the contact resistance of the semiconductor device.

Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

Abstract: Embodiments of the invention are directed to a method of forming an interconnect structure. A non-limiting example of the method includes forming a transistor over a substrate, forming a dielectric region over the transistor and the substrate, and forming a trench positioned in the dielectric region and over a source or drain (S/D) region of the transistor, wherein a sidewall of the trench includes a gate spacer of the transistor. A volume of the trench is increased by removing the gate spacer from the sidewall of the trench. A first liner and a conductive plug are deposited within a bottom portion of the trench.

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

Abstract: A semiconductor structure is provided that includes a first FinFET device for low power applications and a second FinFET device for non-low power applications. The first FinFET device has an active fin height, i.e., channel height, which is less that an active fin height of the second FinFET device. The active fin height adjustment is achieved utilizing an isolation structure that has a constant height in the region including the first FinFET device and the region including the second FinFET device.

Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.

Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, and a bottom substrate portion formed from a same material as an underlying substrate. An isolation dielectric layer is formed between and around the bottom substrate portion of the one or more fins. A single oxide layer is formed in direct contact with the bottom substrate portion of each fin, between the bottom substrate portion of each fin and the isolation dielectric layer. A gate dielectric is formed over the one or more fins and between a straight sidewall of at least a top portion of the single oxide layer and an adjacent sidewall of the one or more fins, in contact with both the straight sidewall and the bottom substrate portion.

Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.

Abstract: A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.

Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.