Patents by Inventor Dechao Guo

Dechao Guo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FIN OXIDATION BY FLOWABLE OXIDE FILL AND STEAM ANNEAL TO MITIGATE LOCAL LAYOUT EFFECTS
    Publication number: 20200083089
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • Protection of low temperature isolation fill
    Patent number: 10586700
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Preserving channel strain in fin cuts
    Patent number: 10573646
    Abstract: A method of forming a semiconductor structure includes forming a fin cut mask over a region in a fin field-effect transistor (finFET) structure. The finFET structure includes one or more fins and one or more gates and source/drain regions formed over the one or more fins in active regions of the finFET structure. The method also includes performing a fin cut by removing a portion of at least one fin. The portion of the at least one fin is determined by an exposed area of the fin cut mask. The exposed area of the fin cut mask includes at least a portion of the at least one fin between a first dummy gate and a second dummy gate formed over the at least one fin. The method further includes removing the fin cut mask and depositing an oxide to replace the portion of the at least one fin removed during the fin cut.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew M. Greene, Dechao Guo, Ravikumar Ramachandran, Rajasekhar Venigalla
  • GATE-ALL-AROUND FETS HAVING UNIFORM THRESHOLD VOLTAGE
    Publication number: 20200043808
    Abstract: A technique relates to a semiconductor device. An N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work function metal, an outer work function metal, a first nanosheet including an inner channel surface having a first threshold voltage, and a second nanosheet including an outer channel surface having a second threshold voltage. The outer work function metal is modified so as to cause the outer channel surface for the second nanosheet to have the second threshold voltage within a predefined amount of the first threshold voltage for the inner channel surface of the first nanosheet, the predefined amount being within about 20 millivolts (mV).
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Ruqiang BAO, Dechao GUO, Junli Wang, Heng WU
  • SEMICONDUCTOR DEVICE HAVING TWO-PART SPACER
    Publication number: 20200035808
    Abstract: Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventors: Ruqiang Bao, Junli Wang, Dechao Guo, Heng Wu, Ernest Y. Wu
  • FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
    Patent number: 10535773
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • Protection of low temperature isolation fill
    Patent number: 10535550
    Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael P. Belyansky, Richard A. Conti, Dechao Guo, Devendra K. Sadana, Jay W. Strane
  • Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS
    Patent number: 10535517
    Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo
  • Forming a sacrificial liner for dual channel devices
    Patent number: 10510892
    Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • Formation of a semiconductor device with selective nitride grown on conductor
    Patent number: 10468412
    Abstract: A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of transistors. An oxide is deposited over the source and drain of the transistors. A block mask is placed over the first transistor, and the oxide is removed from the second transistor. The block mask is removed and an epitaxial growth is performed on the second transistor. A selective nitridation is performed on the second transistor, and the process is repeated for the first transistor. Other embodiments are also described.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: November 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Zuoguang Liu
  • Interface Charge Reduction for SiGe Surface
    Publication number: 20190326429
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen w. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS
    Publication number: 20190295844
    Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.
    Type: Application
    Filed: March 23, 2018
    Publication date: September 26, 2019
    Inventors: Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo
  • Interface charge reduction for SiGe surface
    Patent number: 10381479
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken
  • ANOMALY DETECTION USING IMAGE-BASED PHYSICAL CHARACTERIZATION
    Publication number: 20190228519
    Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Inventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
  • Low-drive current FinFET structure for improving circuit density of ratioed logic in SRAM devices
    Patent number: 10361210
    Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Dechao Guo, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Replacement metal gate scheme with self-alignment gate for vertical field effect transistors
    Patent number: 10355106
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Raqiang Bao, Dechao Guo
  • Integrated metal gate CMOS devices
    Patent number: 10332883
    Abstract: A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Forming a sacrificial liner for dual channel devices
    Patent number: 10312370
    Abstract: Semiconductor devices and methods of forming the same include forming a liner over one or more channel fins on a substrate. An etch is performed down into the substrate using the one or more channel fins and the liner as a mask to form a substrate fin underneath each of the one or more channel fins. An area around the one or more channel fins and substrate fins is filled with a flowable dielectric. The flowable dielectric is annealed to solidify the flowable dielectric. The anneal oxidizes at least a portion of sidewalls of each substrate fin, such that each substrate fin is narrower in the oxidized portion than in a portion covered by the liner.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • FINFET WITH SIGMA RECESSED SOURCE/DRAIN AND UN-DOPED BUFFER LAYER EPITAXY FOR UNIFORM JUNCTION FORMATION
    Publication number: 20190157457
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 23, 2019
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • Threshold voltage modulation through channel length adjustment
    Patent number: 10263098
    Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou