Abstract: A light-emitting integrated wafer structure, comprising: three overlying layers, wherein each of the three overlying layers emits light at a different wavelength and wherein at least one of the three overlying layers is transferred to the light-emitting integrated wafer structure using one of atomic species implants assisted cleaving, laser lift-off, etch-back, or chemical-mechanical-polishing (CMP).

Abstract: A method for fabricating a light-emitting integrated device, comprises overlying three layers, wherein each of the three layers emits light at a different wavelength, and wherein the overlying comprises one of: performing an atomic species implantation, performing a laser lift-off, performing an etch-back, or chemical-mechanical polishing (CMP).

Abstract: A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; preparing a second monocrystalline layer comprising semiconductor regions overlying the first monocrystalline layer; and etching portions of said first monocrystalline layer and portions of said second monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising: a first monocrystalline layer comprising semiconductor regions, overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer comprising semiconductor regions overlying the isolation layer; and etching portions of the first monocrystalline layer as part of forming at least one transistor on said first monocrystalline layer.

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.

Abstract: A storage system and method for operating the storage system that uses reversible resistance-switching elements is described. Techniques are disclosed herein for varying programming conditions to account for different resistances that memory cells have. These techniques can program memory cells in fewer attempts, which can save time and/or power. Techniques are disclosed herein for achieving a high programming bandwidth while reducing the worst case current and/or power consumption. In one embodiment, a page mapping scheme is provided that programs multiple memory cells in parallel in a way that reduces the worst case current and/or power consumption.

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract: A method of manufacturing a semiconductor wafer, the method comprising providing a base wafer comprising a semiconductor substrate; preparing a first monocrystalline layer comprising semiconductor regions; performing a first layer transfer of the first monocrystalline layer on top of the semiconductor substrate; preparing a second monocrystalline layer comprising semiconductor regions; performing a second layer transfer of the second monocrystalline layer on top of the first monocrystalline layer; and etching portions of the first monocrystalline layer and portions of the second monocrystalline layer.

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks and at least one of the second alignment marks.

Abstract: A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.

Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks in a first direction and at least one of the second alignment marks in a second direction.

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.

Abstract: Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air brake. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element.

Abstract: During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation.

Abstract: A non-volatile resistance-switching memory element includes a resistance-switching element formed from a metal oxide layer having a dopant which is provided at a relatively high concentration such as 10% or greater. Further, the dopant is a cation having a relatively large ionic radius such as 70 picometers or greater, such as Magnesium, Chromium, Calcium, Scandium or Yttrium. A cubic fluorite phase lattice may be formed in the metal oxide even at room temperature so that switching power may be reduced. The memory element may be pillar-shaped, extending between first and second electrodes and being in series with a steering element such as a diode. The metal oxide layer may be deposited at the same time as the dopant. Or, using atomic layer deposition, an oxide of a first metal can be deposited, followed by an oxide of a second metal, followed by annealing to cause intermixing, in repeated cycles.

Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.