Patents by Inventor Deepak C. Sekar

Deepak C. Sekar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and structure for heat removal
    Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • NOVEL 3D SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20150061036
    Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; at least one contact to the second transistors, where the at least one contact has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; a second set of external connections overlying the second layer to connect the device to external devices; and an interconnection layer in-between the first layer and the second layer, where the interconnection layer includes copper or aluminum.
    Type: Application
    Filed: October 8, 2014
    Publication date: March 5, 2015
    Applicant: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Method of manufacturing a semiconductor device with two monocrystalline layers
    Patent number: 8956959
    Abstract: A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: February 17, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach
  • System comprising a semiconductor device and structure
    Patent number: 8907442
    Abstract: A semiconductor device, including: a first layer including first transistors; an interconnection layer overlying the first transistors, the interconnection layer providing interconnection for the first transistors; a bonding layer overlying the interconnection layer; a second layer overlying the bonding layer; and a carrier substrate for the transferring of the second layer, where the second layer includes at least one through second layer via, where the at least one through second layer via has a diameter of less than 100 nm, where the second layer includes a plurality of second transistors, and where the second layer is transferred from a donor wafer.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: December 9, 2014
    Assignee: Monolthic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar, Zeev Wurman
  • Semiconductor device and structure for heat removal
    Patent number: 8901613
    Abstract: A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.
    Type: Grant
    Filed: March 6, 2011
    Date of Patent: December 2, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach, Brian Cronquist
  • Semiconductor and optoelectronic devices
    Patent number: 8823122
    Abstract: An integrated device, the device including a first crystalline layer covered by an oxide layer, a second crystalline layer overlying the oxide layer, wherein the first and second crystalline layers are image sensor layers, and the device includes a third crystalline layer, wherein the third crystalline layer includes single crystal transistors.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 2, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Monolithic three-dimensional semiconductor device and structure
    Patent number: 8754533
    Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: June 17, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
  • Method for fabricating novel semiconductor and optoelectronic devices
    Patent number: 8753913
    Abstract: A method for fabricating an integrated device, the method including, overlying a first crystalline layer onto a second crystalline layer to form a combined layer, wherein one of the first and second crystalline layers is an image sensor layer and at least one of the first and second crystalline layers has been transferred by performing an atomic species implantation, and wherein at least one of the first and second crystalline layers includes single crystal transistors.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 17, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar
  • Method for fabrication of a semiconductor device and structure
    Patent number: 8709880
    Abstract: A method of manufacturing semiconductor devices: providing a first device including a first die and second die, where the first die is diced from a first wafer, the second die is diced from a second wafer, the first die is connected to the second die using at least one through-silicon-via; providing a second device including a third die and fourth die, where the third die is diced from a third wafer, the fourth die is diced from a fourth wafer, the third die is connected to the fourth die using at least one through-silicon-via; where the first die includes a first functionality and the third die includes a second functionality, the first functionality is different than the second functionality, a majority of the masks used for processing the first wafer and the third wafer are the same; and the second die size is substantially different than the fourth die size.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 29, 2014
    Assignee: Monolithic 3D Inc
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Semiconductor device and structure
    Patent number: 8687399
    Abstract: An Integrated device comprising a first monocrystalline layer comprising logic circuit regions and a second monocrystalline layer comprising memory regions constructed above first monocrystalline layer, wherein the memory regions comprise second transistors, wherein said second transistors comprise drain and source that are horizontally oriented with respect to the second monocrystalline layer, and a multiplicity of vias through the second monocrystalline layer providing connections between the memory regions and the logic circuit regions, wherein at least one of the multiplicity of vias have a radius of less than 100 nm.
    Type: Grant
    Filed: October 2, 2011
    Date of Patent: April 1, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C Sekar, Zvi Or-Bach, Paul Lim
  • Structure and fabrication method for resistance-change memory cell in 3-D memory
    Patent number: 8686419
    Abstract: A memory device in a 3-D read and write memory includes a resistance-changing layer, and a local contact resistance in series with, and local to, the resistance-changing layer. The local contact resistance is established by a junction between a semiconductor layer and a metal layer. Further, the local contact resistance has a specified level of resistance according to a doping concentration of the semiconductor and a barrier height of the junction. A method for fabricating such a memory device is also presented.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: April 1, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Franz Kreupl, Deepak C Sekar
  • Method for fabrication of configurable systems
    Patent number: 8664042
    Abstract: A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: March 4, 2014
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong
  • Optimized electrodes for Re-RAM
    Patent number: 8637845
    Abstract: Optimized electrodes for ReRAM memory cells and methods for forming the same are discloses. One aspect comprises forming a first electrode, forming a state change element in contact with the first electrode, treating the state change element, and forming a second electrode. Treating the state change element increases the barrier height at the interface between the second electrode and the state change element. Another aspect comprises forming a first electrode in a manner to deliberately establish a certain degree of amorphization in the first electrode, forming a state change element in contact with the first electrode. The degree of amorphization of the first electrode is either at least as great as the degree of amorphization of the state change element or no more than 5 percent less than the degree of amorphization of the state change element.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: January 28, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Deepak C. Sekar, April Schricker, Xiying Chen, Klaus Schuegraf
  • 3D memory semiconductor device and structure
    Patent number: 8581349
    Abstract: A 3D memory device, including: a first memory layer including a first memory transistor with side gates; a second memory layer including a second memory transistor with side gates; and a periphery circuits layer including logic transistors for controlling the memory, the periphery circuits are covered by a first isolation layer, where the first memory layer includes a first monolithically mono-crystal layer directly bonded to a second isolation layer, and the second memory layer includes a second monolithically mono-crystal layer directly bonded to the second isolation layer, and the first mono-crystal layer is bonded on top of the first isolation layer, and the second memory transistor is self-aligned to the first memory transistor.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: November 12, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Deepak C. Sekar, Zvi Or-Bach, Brian Cronquist
  • Punch-through diode steering element
    Patent number: 8575715
    Abstract: A storage system and method for forming a storage system that uses punch-through diodes as a steering element in series with a reversible resistivity-switching element is described. The punch-through diode allows bipolar operation of a cross-point memory array. The punch-through diode may have a symmetrical non-linear current/voltage relationship. The punch-through diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in cross-point memory arrays having resistive switching elements. The punch-through diode may be a N+/P?/N+ device or a P+/N?/P+ device.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: November 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Andrei Mihnea, Deepak C. Sekar, George Samachisa, Roy Scheuerlein, Li Xiao
  • Method for fabrication of a semiconductor device and structure
    Patent number: 8557632
    Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 15, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20130267046
    Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
    Type: Application
    Filed: April 9, 2012
    Publication date: October 10, 2013
    Inventors: Zvi OR-BACH, Deepak C. SEKAR, Brian CRONQUIST
  • Semiconductor device and structure
    Patent number: 8541819
    Abstract: A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: September 24, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, Jan Lodewijk de Jong, Deepak C. Sekar
  • NOVEL SEMICONDUCTOR DEVICE AND STRUCTURE
    Publication number: 20130241026
    Abstract: A device including a first layer of first transistors interconnected by at least one first interconnection layer, wherein the first interconnection layer includes copper or aluminum, a second layer including second transistors, the second layer overlaying the first interconnection layer, wherein the second layer is less than 2 micron thick, wherein the second layer has a coefficient of thermal expansion; and a connection path connecting at least one of the second transistors to the first interconnection layer, wherein the connection path includes at least one through-layer via, and wherein the through-layer via includes material whose co-efficient of thermal expansion is within 50 percent of the second layer coefficient of thermal expansion.
    Type: Application
    Filed: March 17, 2012
    Publication date: September 19, 2013
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Method of manufacturing a semiconductor device and structure
    Patent number: 8536023
    Abstract: A method of manufacturing semiconductor wafers, the method including: providing a donor wafer including a semiconductor substrate; performing a lithography step and processing the donor wafer; and performing at least two subsequent steps of layer transfer out of the donor wafer, each layer transfer step producing a transferred layer, where each of the transferred layers had been affected by the lithography step, and where each of the transferred layer includes a plurality of transistors with side gates, and where the layer transfer includes an ion-cut, the ion-cut including an ion implant thru the transistors.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: September 17, 2013
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist