Patents by Inventor Deepak Kulkarni

Deepak Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153745
    Abstract: Semiconductor fabrication component preparation methods are described. In embodiments, the methods include forming a first layer on a surface of the semiconductor fabrication component. The first layer is characterized by a porosity of greater than or about 0.01 vol. %. The methods further include depositing a second layer on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol. %. Treated semiconductor fabrication components are also described. In embodiments, the treated components include a first layer formed in the surface of the semiconductor fabrication component, where the first layer is characterized by a porosity of greater than or about 0.01 vol. %., and a second layer positioned on the first layer, where the second layer is characterized by a porosity of less than or about 20 vol. %.
    Type: Application
    Filed: November 5, 2022
    Publication date: May 9, 2024
    Inventors: Katherine Woo, Jennifer Y. Sun, Jian Li, Wenhao Zhang, Mayur Govind Kulkarni, Chidambara A. Ramalingam, Ryan Sheil, Martin J. Seamons, Nitin Deepak
  • Patent number: 11973041
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Publication number: 20230343774
    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI
  • Patent number: 11769735
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
  • Publication number: 20230287600
    Abstract: The current invention discloses an enzyme-based method for making high quality textile fibres from plant derived biomass. The invention discloses a method for production of high-quality textile grade fibres that have no loss in quality parameters as compared to textile grade fibres made from cellulosic biomass by conventional methods that use harsh chemical treatments. The fibres produced by this method from raw natural fibres can be spun into yarn by automated procedures and the yarn can be woven into high quality fabrics by powerloom as well as handloom.
    Type: Application
    Filed: July 2, 2021
    Publication date: September 14, 2023
    Inventors: Rashmi CHOWDHARY, Anshika AGARWAL, Nitin SHETYE, Deepak KULKARNI
  • Patent number: 11675932
    Abstract: A computer-implemented method includes receiving permission data from an application server. The permission data is for an account to access a software application of a plurality of software applications, and the application server is configured to provide the software application. Responsive to receiving the permission data from the application server, storing the permission data in a native database. Receiving a request to grant the account access to the software application. Determining whether the database stores the permission data for the account to access the software application. In response to determining that the database stores the permission data, granting access to the account to access the software application.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: June 13, 2023
    Assignees: ATLASSIAN PTY LTD., ATLASSIAN US, INC.
    Inventors: Jeffrey Lawrence Farber, Sidney Gee-Lake Shek, Pramod Shashidhara, Deepak Kulkarni, Jonathan Paul Gilbert
  • Publication number: 20230130944
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 27, 2023
    Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
  • Publication number: 20230040850
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 9, 2023
    Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
  • Patent number: 11515248
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: November 29, 2022
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Publication number: 20220364742
    Abstract: The present disclosure is directed to a sunshade system that monitors a position of the sun and adjusts a position of a frame and/or blades based on a position of the sun. For example, a heating, ventilation, and air conditioning (HVAC) unit of an HVAC system may be exposed to adverse, external weather conditions, such as sunlight, which may heat up components of the HVAC unit and decrease an efficiency of the HVAC system. Accordingly, a control system of the sunshade system may monitor the position of the sun and adjust the position of the frame and/or the blades to provide adequate shading for the HVAC unit.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 17, 2022
    Inventors: Akash Manoji, Vikas Patil, Amey Deepak Kulkarni, Ashish Shoukat Naikwade, Joseph S. Rockhold, Dino Randy Smith, JR., Ravindra Warake, Suvam Saha, Melissa M. Massar
  • Publication number: 20220238506
    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 28, 2022
    Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni
  • Publication number: 20220238458
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Application
    Filed: April 8, 2022
    Publication date: July 28, 2022
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI, Rahul MANEPALLI, Xiaoying GUO
  • Publication number: 20220199503
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE
  • Publication number: 20220164461
    Abstract: A computer-implemented method includes receiving permission data from an application server. The permission data is for an account to access a software application of a plurality of software applications, and the application server is configured to provide the software application. Responsive to receiving the permission data from the application server, storing the permission data in a native database. Receiving a request to grant the account access to the software application. Determining whether the database stores the permission data for the account to access the software application. In response to determining that the database stores the permission data, granting access to the account to access the software application.
    Type: Application
    Filed: February 11, 2022
    Publication date: May 26, 2022
    Inventors: Jeffrey Lawrence Farber, Sidney Gee-Lake Shek, Pramod Shashidhara, Deepak Kulkarni, Jonathan Paul Gilbert
  • Publication number: 20220115367
    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI
  • Publication number: 20220115334
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI, Rahul MANEPALLI, Xiaoying GUO
  • Publication number: 20220084013
    Abstract: A digital asset system comprises a user information system, a transaction machine instructions generator to produce machine instructions of a blockchain transaction, a signing module, a blockchain communications system that sends system-signed messages to a blockchain system, and a transaction mediating system that receives user input comprising a transaction data structure representing the blockchain transaction. The transaction mediating system can send machine instructions to other elements of the system in response to user input and machine instructions of the blockchain transaction for execution on a blockchain system.
    Type: Application
    Filed: January 21, 2020
    Publication date: March 17, 2022
    Inventors: Dhruva Deepak KULKARNI, Mateusz Wojciech POSPIESZNY, Pramod MADABHUSHI
  • Patent number: 11263348
    Abstract: A computer-implemented method includes receiving permission data from an application server. The permission data is for an account to access a software application of a plurality of software applications, and the application server is configured to provide the software application. Responsive to receiving the permission data from the application server, storing the permission data in a native database. Receiving a request to grant the account access to the software application. Determining whether the database stores the permission data for the account to access the software application. In response to determining that the database stores the permission data, granting access to the account to access the software application.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: March 1, 2022
    Assignees: ATLASSIAN PTY LTD., ATLASSIAN INC.
    Inventors: Jeffrey Lawrence Farber, Sidney Gee-Lake Shek, Pramod Shashidhara, Deepak Kulkarni, Jonathan Paul Gilbert
  • Publication number: 20210357927
    Abstract: Methods and systems are provided authenticating transactions on a token contract. A transaction rule compliance engine that utilizes stored user information to ensure that transactions of tokens associated with the token contract comply with defined ruleset. A curation system maintains the stored user information on the token contract or elsewhere on the blockchain system.
    Type: Application
    Filed: September 17, 2019
    Publication date: November 18, 2021
    Inventors: David Ben Kita, David Charles Williams, Dhruva Deepak Kulkarni, Mateusz Wojciech Pospieszny, Pramod Madabhushi
  • Publication number: 20200395297
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN