Patents by Inventor Deepak Kulkarni
Deepak Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12181164Abstract: The present disclosure is directed to a sunshade system that monitors a position of the sun and adjusts a position of a frame and/or blades based on a position of the sun. For example, a heating, ventilation, and air conditioning (HVAC) unit of an HVAC system may be exposed to adverse, external weather conditions, such as sunlight, which may heat up components of the HVAC unit and decrease an efficiency of the HVAC system. Accordingly, a control system of the sunshade system may monitor the position of the sun and adjust the position of the frame and/or the blades to provide adequate shading for the HVAC unit.Type: GrantFiled: May 17, 2021Date of Patent: December 31, 2024Assignee: AIR DISTRIBUTION TECHNOLOGIES IP, LLCInventors: Akash Manoji, Vikas Patil, Amey Deepak Kulkarni, Ashish Shoukat Naikwade, Joseph S. Rockhold, Dino Randy Smith, Jr., Ravindra Warake, Suvam Saha, Melissa M. Massar
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Publication number: 20240427907Abstract: A method, computer program product, and computer system for clustering data objects. Data objects are accessed. The data objects are sorted. The data objects are transformed into binary words. The binary words are encoded into blocks, using the sorted data objects. Block clusters are generated from the blocks. The block clusters are converted into word clusters. For each word cluster, the word cluster is reconfigured into L word clusters in a manner that minimizes a total number of binary word deviations in the L word clusters, wherein L is at least 1.Type: ApplicationFiled: June 26, 2023Publication date: December 26, 2024Inventors: Pedro Miguel Barbas, Deepak Kulkarni, Christian Cesar Bones, Guilherme Rodrigues de Abreu, Rodrigo Cravo Dorea Arnez
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Publication number: 20240421073Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: August 28, 2024Publication date: December 19, 2024Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Publication number: 20240386358Abstract: An embodiment for improved insight discovery using combinatorial low-dimensional clustering. The embodiment may detect a set of data point key performance indicators (KPIs) from one or more statistical or machine learning domain spaces. The embodiment may generate clusters including a series of binary vectors corresponding to the detected set of data point KPIs, wherein neighboring binary vectors having a mutual Mahalanobis distance below a threshold value are clustered together. The embodiment may generate weighted binary matrix representations of the generated clusters The embodiment may perform insight discovery by identifying data point intersections within the generated weighted binary matrix representations.Type: ApplicationFiled: May 19, 2023Publication date: November 21, 2024Inventors: Pedro Miguel Barbas, Clara Liu, DEEPAK KULKARNI, Navneet Dalipkum Magotra, Christian Cesar Bones
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Patent number: 12107042Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: October 24, 2022Date of Patent: October 1, 2024Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20240250043Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.Type: ApplicationFiled: March 15, 2024Publication date: July 25, 2024Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI, Rahul MANEPALLI, Xiaoying GUO
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Patent number: 11990427Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.Type: GrantFiled: April 8, 2022Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
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Patent number: 11984396Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: December 27, 2022Date of Patent: May 14, 2024Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Patent number: 11973041Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.Type: GrantFiled: December 20, 2021Date of Patent: April 30, 2024Assignee: Intel CorporationInventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
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Publication number: 20230343774Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.Type: ApplicationFiled: June 29, 2023Publication date: October 26, 2023Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI
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Patent number: 11769735Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.Type: GrantFiled: February 12, 2019Date of Patent: September 26, 2023Assignee: Intel CorporationInventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni, Rahul Manepalli, Xiaoying Guo
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Publication number: 20230287600Abstract: The current invention discloses an enzyme-based method for making high quality textile fibres from plant derived biomass. The invention discloses a method for production of high-quality textile grade fibres that have no loss in quality parameters as compared to textile grade fibres made from cellulosic biomass by conventional methods that use harsh chemical treatments. The fibres produced by this method from raw natural fibres can be spun into yarn by automated procedures and the yarn can be woven into high quality fabrics by powerloom as well as handloom.Type: ApplicationFiled: July 2, 2021Publication date: September 14, 2023Inventors: Rashmi CHOWDHARY, Anshika AGARWAL, Nitin SHETYE, Deepak KULKARNI
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Patent number: 11675932Abstract: A computer-implemented method includes receiving permission data from an application server. The permission data is for an account to access a software application of a plurality of software applications, and the application server is configured to provide the software application. Responsive to receiving the permission data from the application server, storing the permission data in a native database. Receiving a request to grant the account access to the software application. Determining whether the database stores the permission data for the account to access the software application. In response to determining that the database stores the permission data, granting access to the account to access the software application.Type: GrantFiled: February 11, 2022Date of Patent: June 13, 2023Assignees: ATLASSIAN PTY LTD., ATLASSIAN US, INC.Inventors: Jeffrey Lawrence Farber, Sidney Gee-Lake Shek, Pramod Shashidhara, Deepak Kulkarni, Jonathan Paul Gilbert
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Publication number: 20230130944Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: December 27, 2022Publication date: April 27, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Publication number: 20230040850Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: ApplicationFiled: October 24, 2022Publication date: February 9, 2023Inventors: Robert STARKSTON, Debendra MALLIK, John S. GUZEK, Chia-Pin CHIU, Deepak KULKARNI, Ravi V. MAHAJAN
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Patent number: 11515248Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.Type: GrantFiled: September 1, 2020Date of Patent: November 29, 2022Assignee: Intel CorporationInventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
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Publication number: 20220364742Abstract: The present disclosure is directed to a sunshade system that monitors a position of the sun and adjusts a position of a frame and/or blades based on a position of the sun. For example, a heating, ventilation, and air conditioning (HVAC) unit of an HVAC system may be exposed to adverse, external weather conditions, such as sunlight, which may heat up components of the HVAC unit and decrease an efficiency of the HVAC system. Accordingly, a control system of the sunshade system may monitor the position of the sun and adjust the position of the frame and/or the blades to provide adequate shading for the HVAC unit.Type: ApplicationFiled: May 17, 2021Publication date: November 17, 2022Inventors: Akash Manoji, Vikas Patil, Amey Deepak Kulkarni, Ashish Shoukat Naikwade, Joseph S. Rockhold, Dino Randy Smith, JR., Ravindra Warake, Suvam Saha, Melissa M. Massar
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Publication number: 20220238458Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a mold layer having a first surface and a second surface opposite the first surface, and a plurality of first dies embedded in the mold layer. In an embodiment, each of the plurality of first dies has a surface that is substantially coplanar with the first surface of the mold layer. In an embodiment, the electronic package further comprises a second die embedded in the mold layer. In an embodiment, the second die is positioned between the plurality of first dies and the second surface of the mold layer.Type: ApplicationFiled: April 8, 2022Publication date: July 28, 2022Inventors: Srinivas PIETAMBARAM, Gang DUAN, Deepak KULKARNI, Rahul MANEPALLI, Xiaoying GUO
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Publication number: 20220238506Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.Type: ApplicationFiled: April 8, 2022Publication date: July 28, 2022Inventors: Srinivas Pietambaram, Gang Duan, Deepak Kulkarni
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Publication number: 20220199503Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate with a die side and a land side. In an embodiment, a pad is on the land side. In an embodiment, a dielectric layer covers sidewalls of the pad, and a surface finish is over an exposed surface of the pad.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Manish DUBEY, Guruprasad ARAKERE, Deepak KULKARNI, Sairam AGRAHARAM, Wei-Lun K. JEN, Numair AHMED, Kousik GANESAN, Amol D. JADHAV, Kyu-Oh LEE