Patents by Inventor Deepanshu Dutta

Deepanshu Dutta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250259685
    Abstract: A computer system is provided that includes a single processing unit and a plurality of high bandwidth flash (HBF) packages that are in electrical communication with the single processing unit. Each of the HBF packages has a plurality of memory dies with arrays of memory cells. The HBF packages have a combined bandwidth during read with the single processing unit of at least 2.7 TB/s. The dies have a power efficiency of no greater than 1.1 pJ/bit.
    Type: Application
    Filed: May 10, 2024
    Publication date: August 14, 2025
    Inventors: Xiang Yang, Deepanshu Dutta, Yan Li, Masaaki Higashitani
  • Publication number: 20250259689
    Abstract: The memory device includes a memory block with an array of memory cells that are arranged in a plurality of word lines. The memory cells are programmed to one bit per memory cell with each memory cell being either in an erased data state or a programmed data state. The memory device also includes circuitry that is configured to determine that the memory cells have experienced significant of read disturb. Without erasing the memory cells, the circuitry is further configured to program the memory cells in the programmed data state directly to higher threshold voltages to increase a threshold voltage margin between the memory cells in the erased data state and the memory cells in the programmed data state.
    Type: Application
    Filed: May 10, 2024
    Publication date: August 14, 2025
    Inventors: Xiang Yang, Wei Cao, Deepanshu Dutta
  • Patent number: 12380954
    Abstract: A method and system for executing a dynamic 1-tier scan on a memory array are provided. The memory array includes a plurality of memory cells organized into a plurality of sub-groups. The dynamic 1-tier scan includes executing an program loop in which cells of a first sub-group are counted to determine whether a numeric threshold is met, and, if the numeric threshold is met with respect to the first sub group, at least one additional program loop is executed in which cells of a second sub-group are counted to determine whether the numeric threshold is met with respect to the second sub-group.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: August 5, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Deepanshu Dutta, Huai-yuan Tseng
  • Patent number: 12354683
    Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: July 8, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Huiwen Xu, Deepanshu Dutta, Bo Lei
  • Patent number: 12354680
    Abstract: The memory device includes at least one memory block with a plurality of memory cells arranged in a plurality of word lines. The memory device includes control circuitry that is configured to program the memory cells of the at least one memory block in a plurality of program loops. The control circuitry is further configured to receive a command to write user data to the memory device. On at least a portion of a selected word line of the plurality of word lines, the control circuitry is configured to perform a smart verify operation to acquire a smart verify programming voltage. After the smart verify programming voltage is acquired, in a plurality of program loops, the control circuitry is configured to program the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: July 8, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Wei Cao, Deepanshu Dutta
  • Publication number: 20250210124
    Abstract: A non-volatile memory is configured to perform multiple leak tests integrated into a pre-erase process for a set (e.g., block) of non-volatile memory cells after the set of non-volatile memory cells have received programming. An inference circuit is configured to use results of the leak tests with a pre-trained model to predict whether the set of non-volatile memory cells will fail.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Xuan Tian, Liang Li, Deepanshu Dutta
  • Patent number: 12334160
    Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: June 17, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Parth Amin, Anubhav Khandelwal, Deepanshu Dutta
  • Patent number: 12327046
    Abstract: A storage device is provided that conditionally performs read refresh in blocks having higher P/E cycles or older programming times, while refraining from performing read refreshes in blocks having lower P/E cycles or recent programming times. The storage device includes a memory and a controller. The memory includes a block having cells. The controller performs a read refresh on the cells when a number of P/E cycles of the block exceeds an age threshold or after a threshold amount time has elapsed since data was programmed in the block. The controller may also refrain from performing read refreshes on the cells until the number of P/E cycles exceeds the age threshold or until a threshold amount of time has elapsed since the data is programmed. As a result, lower BER may occur due to wider Vt margins, while power and system overhead may be saved.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: June 10, 2025
    Assignee: SANDISK TECHNOLOGIES, INC.
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta, Abhijith Prakash
  • Publication number: 20250156095
    Abstract: A memory apparatus includes memory cells connected to word lines and operable in one of a first read condition in which a word line voltage of the word lines is discharged and a second read condition in which the word line voltage of the word lines is coupled up to a residual voltage level. A control means is coupled to the word lines and is configured to program the memory cells in a program operation. Following programming of the memory cells connected to specific ones of the word lines, the control means is also configured to apply a predetermined dummy read voltage to the specific ones of the word lines during a dummy read operation to maintain the memory cells connected thereto in the second read condition, the specific ones of the word lines determined based on an amount of the memory cells that are programmed.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 15, 2025
    Inventors: Abu Naser Zainuddin, Xiang Yang, Jiahui Yuan, Deepanshu Dutta
  • Publication number: 20250104777
    Abstract: A non-volatile memory comprises a plurality of non-volatile memory cells positioned in different regions of a block of non-volatile memory cells. Each region is connected to a different separate and independently controlled selection line so that each of the regions can be selected (e.g., one at a time) for a memory operation. To perform a read operation, the memory system is configured to apply a voltage to a selected word line and sequentially sense data from non-volatile memory cells positioned in the different regions without recharging the voltage applied to the selected word line.
    Type: Application
    Filed: September 21, 2023
    Publication date: March 27, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Jiahui Yuan, Deepanshu Dutta
  • Patent number: 12254931
    Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Deepanshu Dutta, Jiacen Guo, Takayuki Inoue, Hua-Ling Hsu
  • Patent number: 12249378
    Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: March 11, 2025
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Sarath Puthenthermadam, Jiahui Yuan
  • Patent number: 12243593
    Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Xiang Yang, Deepanshu Dutta, Ohwon Kwon, James Kai, Yuki Mizutani
  • Publication number: 20250046386
    Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Jiahui Yuan, Jiacen Guo, Deepanshu Dutta
  • Patent number: 12198765
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: January 14, 2025
    Inventors: Xiang Yang, Chin-Yi Chen, Deepanshu Dutta
  • Publication number: 20240428874
    Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.
    Type: Application
    Filed: August 7, 2023
    Publication date: December 26, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Huiwen Xu, Deepanshu Dutta, Ken Oowada, Bo Lei, Ravi J. Kumar, Sujjatul Islam, Xue Pitner
  • Publication number: 20240347122
    Abstract: A memory package includes a plurality of memory dies, each of which has a plurality of memory blocks with arrays of memory cells. The memory dies include user data dies that contain user data and an XOR die that contains XOR data. The memory package also includes circuitry for reading the user data and the XOR data. The circuitry is configured to detect a read error during a read operation in a failed die of the plurality of user data dies and read some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die. The circuitry is also configured to perform a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Inventors: Xiang Yang, Deepanshu Dutta, Luca Fasoli
  • Patent number: 12112800
    Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: October 8, 2024
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Deepanshu Dutta, Muhammad Masuduzzaman, Jiacen Guo
  • Publication number: 20240290395
    Abstract: Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.
    Type: Application
    Filed: July 27, 2023
    Publication date: August 29, 2024
    Applicant: SanDisk Technologies LLC
    Inventors: Abu Naser Zainuddin, Jiahui Yuan, Deepanshu Dutta
  • Publication number: 20240282358
    Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.
    Type: Application
    Filed: July 21, 2023
    Publication date: August 22, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Yi Song, Jiahui Yuan, Deepanshu Dutta