Patents by Inventor Deepanshu Dutta

Deepanshu Dutta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456333
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: September 27, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yu-Chung Lien, Jiahui Yuan, Deepanshu Dutta, Christopher Petti
  • Patent number: 11437110
    Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 6, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Fanqi Wu, Deepanshu Dutta, Huai-Yuan Tseng
  • Patent number: 11423993
    Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: August 23, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Zhiping Zhang, Muhammad Masuduzzaman, Huai-Yuan Tseng, Peng Zhang, Dengtao Zhao, Deepanshu Dutta
  • Patent number: 11417400
    Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: August 16, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
  • Publication number: 20220254416
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Ravi Kumar, Deepanshu Dutta, Vishwanath Basavaegowda Shanthakumar
  • Patent number: 11409443
    Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: August 9, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ravi Kumar, Deepanshu Dutta, Niles Yang, Mark Shlick
  • Patent number: 11404127
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: August 2, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Ravi Kumar, Deepanshu Dutta, Vishwanath Basavaegowda Shanthakumar
  • Patent number: 11398280
    Abstract: A method for a pre-lockout read for a reverse order read operation with lockout mode is disclosed. The method comprises: performing a pre-lockout read at a first sensing level to determine which memory cells of the set of memory cells are on in response to the first sensing level being applied to a selected word line; performing a first sensing operation on the selected word line at a second sensing level including sensing memory cells of the set of memory cells determined to be off in response to the pre-lockout read; and performing a second sensing operation on the selected word line at a third sensing level including sensing memory cells of the set of memory cells determined to be on in response to the pre-lockout read, where the first sensing level is of a value between the second sensing level and the third sensing level.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: July 26, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Huai-yuan Tseng, Ravi Kumar
  • Publication number: 20220229588
    Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Deepanshu Dutta, James Kai, Johann Alsmeier, Jian Chen
  • Patent number: 11385810
    Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Deepanshu Dutta, Huai-Yuan Tseng
  • Publication number: 20220208285
    Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Ravi Kumar, Deepanshu Dutta
  • Patent number: 11361834
    Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 14, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Ravi Kumar, Deepanshu Dutta
  • Publication number: 20220171541
    Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.
    Type: Application
    Filed: February 17, 2021
    Publication date: June 2, 2022
    Inventors: Ravi Kumar, Deepanshu Dutta, Niles Yang, Mark Shlick
  • Publication number: 20220165342
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Deepanshu Dutta, Ravi Kumar
  • Publication number: 20220165341
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Applicant: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Dengtao Zhao, Deepanshu Dutta, Ravi Kumar
  • Patent number: 11342035
    Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: May 24, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xue Bai Pitner, Deepanshu Dutta, Ravi Kumar
  • Patent number: 11342033
    Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a data retention compensation scheme; and perform a read operation on the selected word line including applying each data retention compensation scheme corresponding to any zones identified.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 24, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yi Song, Deepanshu Dutta, Huai-yuan Tseng
  • Patent number: 11335413
    Abstract: Aspects of a storage device including a memory and a controller are provided which allow for reduction of current in open blocks during read operations using read voltage ramp rate control. The controller determines whether a block is open or closed. If the block is closed, the controller causes a read voltage to be applied to one of the block's word lines at a first ramp rate. If the block is open, the controller causes a read voltage to be applied to another of the block's word lines at a slower, second ramp rate. The controller further causes a read voltage to be applied to another word line of the open block at a different, third ramp rate. Thus, read voltages for open blocks may ramp slower than read voltages for closed blocks, as well as ramp at different rates for different word lines in open blocks.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: May 17, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yu-Chung Lien, Huai-Yuan Tseng, Deepanshu Dutta
  • Patent number: 11322213
    Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: May 3, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Muhammad Masuduzzaman, Deepanshu Dutta
  • Patent number: 11302409
    Abstract: A storage device is disclosed herein. The storage device comprises a block including a plurality of memory cells and a circuit coupled to the plurality of memory cells of the block. The circuit is configured to program memory cells of a plurality of strings of a word line of the block and verify, for a plurality of sets of the memory cells, a data state of a set of the memory cells, where each set of the plurality of sets of the memory cells includes a memory cell from each string of the plurality of strings of the word line. Further, the circuit is configured to determine a number of sets of the plurality of memory cell sets that are verified to be in a first data state and determine, based on the number of sets, whether the block is faulty.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 12, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Xue Pitner, Deepanshu Dutta, Huai-Yuan Tseng, Ravi Kumar, Cynthia Hsu