Abstract: A non-volatile memory comprises a plurality of non-volatile memory cells positioned in different regions of a block of non-volatile memory cells. Each region is connected to a different separate and independently controlled selection line so that each of the regions can be selected (e.g., one at a time) for a memory operation. To perform a read operation, the memory system is configured to apply a voltage to a selected word line and sequentially sense data from non-volatile memory cells positioned in the different regions without recharging the voltage applied to the selected word line.

Abstract: An apparatus is provided that includes a plurality of memory cells, logic circuits coupled to the memory cells and configured to store 4-bit data in each of the memory cells, and a control circuit coupled to the memory cells and the logic circuits. The control circuit configured to cause the logic circuits to store 3-bit data in each of the memory cells.

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

Abstract: The memory device includes a chip with circuitry, a plurality of memory blocks, and a plurality of bit lines. The memory blocks include an array of memory cells, and the circuitry either overlies or underlies the array of memory cells. The bit lines are divided into two portions that are electrically connected with one another via at least one transistor so that at least one portion of each bit line can be charged independently of the other portion of the same bit line.

Abstract: When performing a read process, a non-volatile memory first performs a pre-read sensing of the condition of memory cells connected to neighbor word lines. While applying a first word line voltage associated with a first programmed data state to the selected word line, the memory system performs two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a first condition and perform two sensing operations for the first programmed data state on selected memory cells that have neighbor memory cells on the neighbor word lines in a second condition. Based on that sensing, the data being stored in the set of selected memory cells is determined. In some embodiments, at least one of the two sensing operations for each condition includes sensing soft bit information that improves the data decoding process.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

Abstract: An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Abstract: A memory package includes a plurality of memory dies, each of which has a plurality of memory blocks with arrays of memory cells. The memory dies include user data dies that contain user data and an XOR die that contains XOR data. The memory package also includes circuitry for reading the user data and the XOR data. The circuitry is configured to detect a read error during a read operation in a failed die of the plurality of user data dies and read some of the user data of the user data dies besides the failed die and reading some of the XOR data of the XOR die. The circuitry is also configured to perform a read recovery operation that includes an XOR operation using, as inputs, the user data of the user data dies besides the failed die and the XOR data of the XOR die.

Abstract: A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.

Abstract: Technology is disclosed herein for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

Abstract: A storage device may be configured to determine data states for a first set of memory cells, of an array of memory cells, that are part of a logical N?1 neighboring word line that is adjacent to a selected word line. The storage device may be further configured to determine a program voltage configuration based on the data states. The storage device may be further configured to determine, using the program voltage configuration, a program operation on the selected word line to iteratively program respective memory cells, of a second set of memory cells that are part of the selected word line. Determining the data states, determining the program voltage configuration, and performing the program operation may be repeated until a program stop condition is satisfied.

Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to perform a programming operation to program a set of memory cells. The control circuitry, when performing the programming operation, may be configured to apply a set of biased program voltages to lines connecting to respective memory cells in an array. The set of biased program voltages may have values that are based on positions of the respective memory cells within the array relative to an outer memory string group of a set of memory string groups.

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

Abstract: The memory device includes a plurality of hybrid memory blocks that can operate in either a single bit per memory cell mode or a multiple bits per memory cell mode. The memory blocks each include a plurality of memory cells, which are arranged in a plurality of word lines. Control circuitry is configured to program a selected word line to an SLC format. The control circuitry is further configured to determine which zone within the selected hybrid memory block the selected word line is located in and set an SLC programming voltage to a level based on the determination of the zone of the selected word line. The control circuitry is further configured to apply a programming pulse at the SLC programming voltage to the selected word line to program the memory cells of the selected word line.

Abstract: A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells disposed in a plurality of planes. The control circuit is configured to concurrently erase a block of memory cells in each of the plurality of planes, determine that the concurrent erase failed, disconnect a first one of the planes from the plurality of planes to form first remaining planes, and concurrently erase a block of memory cells in each of the first remaining planes.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells connected to one of a plurality of word lines and disposed in memory holes coupled to bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the bit lines and for a group of the memory cells divided into a plurality of subsets, is configured to determine whether comparatively fewer read errors of the memory cells arise while pre-charging ones of the bit lines associated with each of the plurality of subsets. The control means is also configured to pre-charge ones of the bit lines associated with one the plurality of subsets with comparatively fewer read errors and read the memory cells associated therewith during a scan operation.