Abstract: Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.

Abstract: A method for detecting and isolating defective memory plane(s) of a non-volatile memory structure during a program verify operation, comprising: initiating, for each plane, a word line verify voltage level scan with a bit scan pass fail criterion and at a starting voltage located within an intended program threshold voltage distribution curve, incrementally decreasing the word line verify voltage by a predetermined offset until a specific condition of the scan is obtained, and storing the voltage at which the specific condition of the scan is obtained, wherein the stored voltage represents a voltage of an upper tail portion of an actual programmed threshold voltage distribution curve of the plane. The stored voltages of all of the memory planes of the structure are compared to determine which plane corresponds to the lowest stored voltage. A “fail” status is applied to the plane corresponding to the lowest stored voltage.

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive word line layers located over a substrate, and a plurality of vertical memory strings. Each vertical memory string includes a series connection of a memory stack structure and a selector element. Each of the memory stack structures extends through the alternating stack and includes a respective memory film and a respective vertical semiconductor channel. Each of the selector elements includes a two terminal device that is configured to provide at least two different resistivity states.

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

Abstract: Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.

Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.

Abstract: A method for a pre-lockout read for a reverse order read operation with lockout mode is disclosed. The method comprises: performing a pre-lockout read at a first sensing level to determine which memory cells of the set of memory cells are on in response to the first sensing level being applied to a selected word line; performing a first sensing operation on the selected word line at a second sensing level including sensing memory cells of the set of memory cells determined to be off in response to the pre-lockout read; and performing a second sensing operation on the selected word line at a third sensing level including sensing memory cells of the set of memory cells determined to be on in response to the pre-lockout read, where the first sensing level is of a value between the second sensing level and the third sensing level.

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

Abstract: An apparatus includes a controller and a plurality of memory dies operable connected to and controlled by the controller. Each of the memory dies draws a current from a current source during a program operation. The controller being configured to receive a clock signal from each of the memory dies; count the number of clock signal received to determine a count value; and dynamically stagger at least one of the memory dies relative to the other memory dies when the count value reaches a maximum count value within a threshold time. The controller operates to dynamically stagger operation of at least one memory die to prevent the group of memory dies from operating synchronously.

Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.

Abstract: A memory device comprising control circuitry configured to apply a first program voltage to a selected word line, wherein a first subset of memory cells of the selected word line, that correspond to a first set of data states, are inhibited from being programmed with the first program voltage, and wherein the first program voltage is applied to a second subset of memory cells corresponding to a second set of data states. The control circuitry is further configured to cause a first voltage of the selected word line to discharge to a second voltage level corresponding to a second program voltage such that the second program voltage is applied to at least the first subset of memory cells. The control circuitry is further configured to perform a verify operation to verify whether the first subset of memory cells and the second subset of memory cells have completed programming.

Abstract: A data storage device including, in one implementation, a non-volatile memory device and a controller coupled to the non-volatile memory device. The non-volatile memory device includes a memory block. The controller is configured to receive a cycle operation request and perform a wear-level mitigation operation in response to receiving the cycle operation request. To perform the wear-level mitigation operation, the controller is configured to determine a read state condition of the memory block, perform the requested cycle operation, and increment a cycle count of the memory block by a value based on the determined read state condition of the memory block. The first read state of the memory block and the second read state of the memory block are based on a wordline voltage that is associated with the memory block.