Patents by Inventor Denny Tang
Denny Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8263959Abstract: A method of manufacturing a memory device is provided. The method includes forming an electrode over a substrate. The method also includes forming an opening in the electrode to provide a tapered electrode contact surface proximate the opening. The method further includes forming a phase change feature over the electrode and on the tapered electrode contact surface.Type: GrantFiled: May 9, 2007Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Hsiung Wang, Li-Shyue Lai, Denny Tang, Wen-Chin Lin
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Patent number: 8213220Abstract: The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction.Type: GrantFiled: January 14, 2010Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Hsu-Chen Cheng, Denny Tang
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Patent number: 8153471Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.Type: GrantFiled: November 14, 2010Date of Patent: April 10, 2012Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Shyue Lai, Chao-Hsiung Wang, Denny Tang, Wen-Chin Lin
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Patent number: 8120947Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: GrantFiled: August 6, 2009Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Patent number: 7964900Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: GrantFiled: September 24, 2009Date of Patent: June 21, 2011Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
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Publication number: 20110059590Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.Type: ApplicationFiled: November 14, 2010Publication date: March 10, 2011Inventors: Li-Shyue Lai, Chao-Hsiung Wang, Denny Tang, Wen-Chin Lin
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Patent number: 7858980Abstract: A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current.Type: GrantFiled: March 1, 2004Date of Patent: December 28, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Shyue Lai, Chao-Hsiung Wang, Denny Tang, Wen-Chin Lin
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Patent number: 7719882Abstract: Disclosed herein is a technique for created an advanced MRAM array for constructing a memory integrated circuit chip. More specifically, the disclosed principles provide for an integrated circuit memory chip comprised of a combination of at least one of an array of high-speed magnetic memory cells, and at least one of an array of high-density magnetic memory cells. Accordingly, a memory chip constructed as disclosed herein provides the benefit of both high-speed and high-density memory cells on the same memory chip. As a result, applications benefiting from the use of (or perhaps even needing) high-speed memory cells are provided by the memory cells in the high-speed memory cell array.Type: GrantFiled: May 2, 2007Date of Patent: May 18, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Hsu-Chen Cheng, Yu-Jen Wang, Denny Tang
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Publication number: 20100118603Abstract: The present disclosure provides a non-volatile memory device. A memory device includes a first magnetic element having a fixed magnetization. The memory device also includes a second magnetic element having a non-fixed magnetization. The memory device further includes a barrier layer between the first and second magnetic elements. A unidirectional current source is electrically coupled to the first and second magnetic elements. The current source is configured to provide a first current to the first and second memory elements. The first current has a first current density and is in a first direction. The current source is also configured to provide a second current to the first and second magnetic elements. The second current has a second current density, different than the first current density, and is in the first direction.Type: ApplicationFiled: January 14, 2010Publication date: May 13, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Hsu-Chen Cheng, Denny Tang
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Patent number: 7688616Abstract: Thus, the present disclosure provides a method of programming a memory array. At least one memory cell including a magnetic element is provided. At least one current source coupled to the magnetic element is provided. A unipolar current is supplied from the at least one current source to the magnetic element at a plurality of non-zero current levels.Type: GrantFiled: June 18, 2007Date of Patent: March 30, 2010Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.Inventors: Yu-Jen Wang, Hsu-Chen Chang, Denny Tang
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Patent number: 7667247Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH3 or CN species.Type: GrantFiled: May 8, 2007Date of Patent: February 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Ya Wang, Wen-Chin Lee, Denny Tang
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Publication number: 20100013020Abstract: A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: ApplicationFiled: September 24, 2009Publication date: January 21, 2010Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, H. C. Cheng
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Publication number: 20090290410Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: ApplicationFiled: August 6, 2009Publication date: November 26, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Patent number: 7622358Abstract: A method for forming semi-insulating portions in a semiconductor substrate provides depositing a hardmask film over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The hardmask is patterned creating openings through which charged particles pass and enter the substrate during an implantation process. The semi-insulating portions may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.Type: GrantFiled: September 30, 2005Date of Patent: November 24, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Chin Lin, Denny Tang, Chuan-Ying Lee, Hsu Chen Cheng
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Patent number: 7599215Abstract: Disclosed herein are toggle-mode magnetoresistive random access memory (MRAM) devices having small-angle toggle write lines, and related methods of toggle-mode switching MRAM devices. Also disclosed are layouts for MRAM devices constructed according to the disclosed principles. Generally speaking, the disclosed principles provide for non-orthogonally aligned toggle-mode write lines used to switch toggle-mode MRAM devices that employ a bias field to decrease the threshold needed to switch the magnetic state of each device. While the conventional toggle-mode write lines provide for the desired orthogonal orientation of the applied magnetic fields to optimize device switching, the use of a bias field affects this orthogonal orientation. By non-orthogonally aligning the two write lines as disclosed herein, the detrimental affect of the bias field may be compensated for such that the net fields applied to the device for both lines are again substantially orthogonal, as is desired.Type: GrantFiled: August 16, 2007Date of Patent: October 6, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chin Lin, Denny Tang, Hsu Chen Cheng
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Patent number: 7579612Abstract: Disclosed herein are new resistive memory devices having one or more buffers layer surrounding a dielectric layer. By inserting one or more buffer layers around the dielectric layer of the device, the resistive ratio of the device is highly enhanced. For example, tests using this unique stack structure have revealed a resistance ratio of approximately 1000× over conventional electrode-dielectric-electrode stack structures found in resistive memory devices. This improvement in the resistance ratio of the resistive memory device is believed to be from the improved interface coherence, and thus smoother topography, between the buffer layer(s) and the dielectric layer.Type: GrantFiled: April 25, 2007Date of Patent: August 25, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Denny Tang, Tai-Bor Wu, Wen-Yuan Chang, Tzyh-Cheang Lee
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Patent number: 7577020Abstract: A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.Type: GrantFiled: October 1, 2007Date of Patent: August 18, 2009Inventors: Shine Chung, Denny Tang, Fu-Lung Hsueh
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Patent number: 7573736Abstract: The present disclosure provides a magnetic memory element. The memory element includes a magnetic tunnel junction (MTJ) element and an electrode. The electrode includes a pinning layer, a pinned layer, and a non-magnetic conductive layer. In one embodiment, the MTJ element includes a first surface having a first surface area, and the electrode includes a second surface. In the embodiment, the second surface of the electrode is coupled to the first surface of the MTJ element such that an interface area is formed and the interface area is less than the first surface area.Type: GrantFiled: May 22, 2007Date of Patent: August 11, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Jen Wang, Denny Tang, Hsu-Chen Cheng
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Patent number: 7545662Abstract: A circuit with an inter-module radiation interference shielding mechanism is disclosed. The circuit includes a circuit module producing a radiation field. At least one radiation shielding module is situated between the circuit module and another module that is vulnerable to the interference of the radiation field. The shielding module is substantially tangential to the radiation field.Type: GrantFiled: March 25, 2005Date of Patent: June 9, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Hsiung Wang, Horng-Huei Tseng, Denny Tang, Wen-Chin Lin, Mark Hsieh
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Publication number: 20090086530Abstract: A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.Type: ApplicationFiled: October 1, 2007Publication date: April 2, 2009Inventors: Shine Chung, Denny Tang, Fu-Lung Hsueh