Abstract: A new process and structure for a multi-sensing level magnetic random access memory (MRAM) cell having different magneto-resistance (MR) ratios includes an improved magnetic tunnel junction (MTJ) configuration. The MTJ configuration includes a first free layer proximate to a first tunneling barrier and a second free layer proximate to a second tunneling barrier and a pinned layer. The first free layer is sandwiched between the first and second tunneling layers. The first tunneling barrier has a MR ratio that differs from a MR ratio of the second tunneling barrier.

Abstract: A magnetic random access memory (MRAM) cell including an MRAM cell stack located over a substrate and first and second write lines spanning opposing termini of the MRAM cell stack. At least one of the first and second write lines includes at least one first portion spanning the MRAM cell stack and at least one second portion proximate the MRAM cell stack. The first and second portions have first and second cross-sectional areas, respectively, wherein the first cross-sectional area is substantially less than the second cross-sectional area.

Abstract: A semiconductor device with a low-k material in close proximity thereto and its fabrication method. The device includes a gate electrode overlying a substrate. An electrically conductive plug is provided immediately adjacent to the gate electrode and making electrical contact to the device. A low-k dielectric material is disposed in the space between the gate electrode and the electrically conductive plug whereby reducing the parasitic capacitance. Thus, higher density of devices can be formed without decreasing operating speed.

Abstract: A magnetic memory device and the method for making same are disclosed. The device uses two metal lines to control a combined magnetic field created thereof. The device has a magnetic memory element connecting to a substrate at a first end thereof, a first metal line connecting to a second end of the magnetic memory element. Further, the device has a second metal line crossing perpendicularly over the first metal line for jointly generating the combined magnetic field, wherein the second metal line is on the side of the second end of the magnetic memory element.

Abstract: Currently it takes up to 10 mA current in the programming line to switch a cell in an MRAM. This current is high enough to cause electro-migration problems over the life of an array so there is a need for a more efficient way to generate the programming field. The present invention solves this problem by (1) passing the programming current inside the cell, i.e, through the pinned layer, and (2) surrounding each program line with a sheath of high permeability material which covers the wire except for a gap located directly above or below the memory element. This high permeability layer may be a conductor or an insulator, the latter case allowing it to make direct contact with the memory element.

Abstract: An MRAM array has groupings of MRAM cells that are interconnected by word control lines, bit lines, primary program control lines, and secondary program control lines. Each MRAM cell is comprised of a magnetic tunnel junction and a primary switching device connected between the magnetic tunnel junction and one of the primary program control lines to provide the write current through the pinned layer of the magnetic tunnel junction. In a first embodiment, the pinned ferromagnetic layer is connected directly to a segmented local program control line that eliminates parasitic currents during read or write of an MRAM cell. In a second embodiment, the MRAM cell includes a secondary switching device connected between the second side of the ferromagnetic layer the local program control line. The secondary program control lines are segmented to eliminate parasitic currents during a read or write of an MRAM cell.

Abstract: In magnetic RAMs a particular memory cell is selected when it is at the intersection of a row and a column of half-selected cells. When data is written into the selected cell, the associated magnetic field can sometimes disturb a neighboring half-selected cell. This restricts the current range available for programming cells. The present invention solves this problem by using two bit lines. One end of the memory cell is connected to a first bit line, in a similar manner to the prior art. However, the programming line does not extend across the full width of the array, being instead connected to a second bit line immediately after it has passed directly across the memory cell. Orthogonal to the two bit lines is a word line whose role is to activate/deactivate transistors associated with the selected cell. Both 1T1R and 2T1R versions of the invention are described.