Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

Abstract: In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.

Abstract: For generation of the multiphase clocks for a serializer, a wide-range multiphase delay-locked loop (DLL) is used in the transmitter to avoid the detrimental characteristics of a phase-locked loop (PLL), such as jitter peaking and accumulated phase error. A tracked 3× oversampling technique with dead-zone phase detection is incorporated in the receiver for robust clock/data recovery in the presence of excessive jitter and inter-symbol interference (ISI). Due to the dead-zone phase detection, phase adjustment is performed only on the tail portions of the transition histogram in the received data eye, thereby exhibiting wide pumping-current range, large jitter tolerance, and small phase error. A voltage-controlled oscillator (VCO), based on a folded starved inverter, shows about 50% less jitter than one with replica bias. The transceiver, implemented in 0.25 &mgr;m CMOS technology, operates at 2.5 GBaud over a 10-m 150-&OHgr; STP cable and at 1.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract: A CMOS low noise amplifier (LNA) is provided that is formed without inductors. The CMOS LNA can be used for a single-chip CMOS RF receiver. The CMOS LNA can include a plurality of amplification stages coupled between an input terminal and an output terminal and a gain controller coupled to each of the plurality of amplifier stages, wherein the CMOS LNA does not include an inductor. Each of the amplification stages can have a symmetrically configured and sized first and second circuits to increase a dynamic range and a feedback loop.

Abstract: A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

Abstract: A new scheme to transfer bidirectional data streams between a digital display and a computer is disclosed. This bidirectional data transfer can make several I/O devices attach to a display. Existing digital display interfaces are usually unidirectional from a computing to a display. Due to the nature of the existing clocking scheme, backward data transfer from the display side to the computer requires a backward clock. This invention discloses a scheme to send data bidirectionally without sending the additional backward clock. This invention also discloses a scheme to tolerate jitters from the clock source. With this approach, this new interface can make a digital display an I/O concentrator.

Abstract: A versatile amplifier circuit for driving a TFT LCD panel is disclosed. The amplifier circuit of the present comprises consists of a complementary input stage, biasing switches, and a rail-to-rail output stage. A signal-transfer switch determines which of two differential amplifiers in the input stage will drive the output stage of the amplifier. A biasing signal precharges a capacitor between the gates of output stage. The rail-to-rail output stage utilizes the precharged capacitor to maintain a voltage required to operate the output stage properly. A polarity signal is used to control the signal-transfer switch. The polarity signal specifies if a lower half of the input stage or an upper half of the input stage is used to drive the output stage of the amplifier circuit. A non-active transistor is kept turned-on above the threshold voltage for quick switching of the output driver. In one embodiment, a coupling capacitor is used between output stage transistors is for this purpose.

Abstract: A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.

Abstract: A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signalis used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A new spread spectrum phase modulation (SSPM) technique is applicable to both data and clock signals. The SSPM technique is more suitable to board level designs than the direct-sequence spread spectrum (DSSS) technique. In addition, SSPM may be combined with controlled edge rate signaling to outperform DSSS.

Abstract: A system for transmission and recovery of original digital data includes an encoder, a transmitter, a receiver, a decoder, and an analog phase locked loop. The analog phase locked loop supplies a sender's clock to the transmitter and a receiver's clock to the receiver, where the sender's clock frequency is a first integer multiple of the system clock frequency, and the receiver's clock frequency is a second integer multiple of the sender's clock frequency within 0.1% tolerance. In a normal flow situation, data frames are output by the receiver in alternate cycles of the system clock. In an overflow situation, data frames are output by the receiver in consecutive cycles of the system clock. In an underflow situation, data frames are not output by the receiver in consecutive cycles of the system clock.