Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively.

Abstract: New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.

Abstract: A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention can include an antenna that receives/transmits RF signals, a PLL that generates multi-phase clock signals having a frequency different from a carrier frequency and a reference signal having the carrier frequency, a demodulation-mixer that mixes the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output signals having a frequency reduced relative to the carrier frequency, two stage amplification that amplifies a selected channel signal to a required dynamic level, and an A/D converting unit for converting the RF signals from the mixing unit into digital signals. The two stage amplification can provide the selected channel signal with sufficient gain, even when an adjacent channel signal is output by the demodulation mixer with greater amplitude or power.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switch network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.

Abstract: A phase lock loop includes a charge pump, a voltage controlled oscillator (VCO), and a phase frequency detector. The phase frequency detector has a dynamic logic structure. The phase frequency detector generates up and down signals for directing the charge pump to provide a voltage signal to the VCO to vary the frequency of the VCO clock. The difference between the up and down signals is indicative of the phase difference between the reference clock signal and the VCO clock. The phase frequency detector includes up and down signal generators for generating the up and down signals, respectively. The up signal generator includes a first p field effect transistor (FET) having a gate for receiving a set signal, a second p FET having a source coupled to the drain of the first p FET and having a gate for receiving a reference clock signal. A first n FET has a source coupled to the drain of the second p FET and has a gate for receiving the set signal.

Abstract: A tuning circuit for an RF communications system and method includes a master block that outputs a control signal to a slave block. The master block can include a first filter having a high pass filter and a low pass filter that each receive the control signal, a first rectifier coupled to the high pass filter, a second rectifier coupled to the low pass filter, and a converter coupled to the first and second rectifiers that outputs the control signal. The first filter is preferably a gm-C poly-phase filter. Output signals of the gm-C poly-phase filter include high and low pass filtering signals resulting from similarly configured circuits so that the output signals have the same electrical characteristics, which results in an increased accuracy, for example, in a cut-off frequency.

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract: A data recovery system for a serial digital data link includes a data sampler, compare logic, a phase controller, and a phase shifter. The data sampler samples input data three times in a bit time which time is determined by clock pulses generated by the phase shifter, and recovers digital data according to a predetermined decision criterion. Data sampling phases are split so as to track the data eye. The compare logic compares the output of the data sampler according to a predetermined method. Phase controller uses the output of the compare logic and generates phase control signals. These signals are set so as to control the sampling times of the data sampler and to attain near optimally recovered data stream. The phase shifter uses the phase control signals and makes three different phase clocks from input clock. The input clock can be an external clock, or can be recovered from the external clock or input data stream.