Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner, and gate spacer layers on side surfaces of the gate structure, the gate spacer layers having an upper surface at a lower height level than an upper surface of the gate electrode layer.

Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the active region, the gate structure including a gate dielectric layer and a gate electrode layer, and the gate electrode layer having a rounded upper corner, and gate spacer layers on side surfaces of the gate structure, the gate spacer layers having an upper surface at a lower height level than an upper surface of the gate electrode layer.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.

Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. A void is present between the silicide layer and the contact plug.

Abstract: A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.

Abstract: A semiconductor device includes an active fin extended in a first direction on a substrate. A gate structure extends in a second direction, wherein the gate structure intersects the active fin and covers an upper portion of the active fin. A source/drain region is positioned on the active fin adjacent to the gate structure. A silicide layer is on the source/drain region. A contact plug is connected to the source/drain region. Avoid is present between the silicide layer and the contact plug.

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.