Patents by Inventor Deok-Han BAE

Deok-Han BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9472653
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: October 18, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Hyuk Kim, Kang-Ill Seo, Hyun-Jae Kang, Deok-Han Bae
  • Publication number: 20160148808
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Jong-Hyuk KIM, Kang-III SEO, Hyun-Jae KANG, Deok-Han BAE
  • Patent number: 9318478
    Abstract: A semiconductor device includes a first dummy gate having a first width, a second dummy gate adjacent to the first dummy gate in a lengthwise direction and having a second width, and a first bridge connecting the first dummy gate and the second dummy gate to each other. The first width and the second width are smaller than a minimum processing line width.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: April 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deok-Han Bae, Dong-Kwon Kim, Jong-Hyuk Kim, Yoon-Moon Park
  • Publication number: 20160087053
    Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 24, 2016
    Inventors: Jin-bum KIM, Chul-sung KIM, Deok-han BAE, Bon-young KOO
  • Publication number: 20160049394
    Abstract: A semiconductor device includes a transistor formed on a substrate and including a gate electrode and a source/drain, an interlayer insulating layer covering the transistor, a first contact hole formed in the interlayer insulating layer to expose a part of the transistor, a first barrier metal conformally formed on an inner surface of the first contact hole, a first conductive layer formed on the first barrier metal to fill the first contact hole, a second contact hole formed on the first conductive layer in the interlayer insulating layer and having a larger width than the first contact hole, a second barrier metal conformally formed on an inner surface of the second contact hole, and a second conductive layer formed on the second barrier metal to fill the second contact hole, wherein the second barrier metal is formed between the first conductive layer and the second conductive layer.
    Type: Application
    Filed: February 23, 2015
    Publication date: February 18, 2016
    Inventors: Heon-Jong SHIN, Deok-Han BAE, Dae-Hee WEON, Hwi-Chan JUN
  • Publication number: 20160020303
    Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.
    Type: Application
    Filed: March 26, 2015
    Publication date: January 21, 2016
    Inventors: Hwi-Chan JUN, Deok-Han BAE, Hyun-Seung SONG, Seung-Seok HA