Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming a vertical fin protruding from the substrate. A buffer oxide liner is formed on a top surface and on sidewalls of the fin. A trench is then formed on the substrate, where at least a portion of the fin protrudes from a bottom surface of the trench. The trench may be formed by forming a dummy gate on at least a portion of the fin, forming an insulation layer on the fin surrounding the dummy gate, and then removing the dummy gate to expose the at least a portion of the fin, such that the trench is surrounded by the insulation layer. The buffer oxide liner is then removed from the protruding portion of the fin, and a gate is formed in the trench on the protruding portion of the fin.

Abstract: Methods for fabricating Fin-Field Effect Transistors (Fin-FETs) are provided. A fin is formed on an integrated circuit substrate. The fin defines a trench on the integrated circuit substrate. A first insulation layer is formed in the trench such that a surface of the first insulation layer is recessed beneath a surface of the fin exposing sidewalls of the fin. A protection layer is formed on the first insulation layer and a second insulation layer is formed on the protection layer in the trench such that protection layer is between the second insulation layer and the sidewalls of the fin. Related Fin-FETs are also provided.

Abstract: A method of forming a fin field effect transistor on a semiconductor substrate includes forming an active region in the substrate, forming an epitaxial layer on the active region, and removing a portion of the epitaxial layer to form a vertical fin on the active region. The fin has a width that is narrower than a width of the active region. Removing a portion of the epitaxial layer may include oxidizing a surface of the epitaxial layer and then removing the oxidized surface of the epitaxial layer to decrease the width of the fin. The epitaxial layer may be doped in situ before removing a portion of the epitaxial layer. The method further includes forming a conductive layer on a top surface and on sidewalls of the fin. Related transistors are also discussed.

Abstract: Integrated circuit field effect transistors include an integrated circuit substrate and a fin that projects away from the integrated circuit substrate, extends along the integrated circuit substrate, and includes a top that is remote from the integrated circuit substrate. A channel region is provided in the fin that is doped a conductivity type and has a higher doping concentration of the conductivity type adjacent the top than remote from the top. A source region and a drain region are provided in the fin on opposite sides of the channel region, and an insulated gate electrode extends across the fin adjacent the channel region.

Abstract: Semiconductor devices have gate structures on a semiconductor substrate with first spacers on sidewalls of the respective gate structures. First contact pads are positioned between the gate structures and have heights lower than the heights of the gate structures. Second spacers are disposed on sidewalls of the first spacers and on exposed sidewalls of the first contact pads. Second contact pads are disposed on the first contact pads.

Abstract: A double gate electrode for a field effect transistor is fabricated by forming in a substrate, a trench and a tunnel that extends from a sidewall of the trench parallel to the substrate. An insulating coating is formed inside the tunnel. A bottom gate electrode is formed within the insulating coating inside the tunnel. An insulating layer is formed on the substrate and a top gate electrode is formed on the insulating layer opposite the bottom gate electrode.

Abstract: Methods of forming thermal oxide layers on a side wall of gate electrodes are disclosed. In particular, thermal oxide layers can be formed on a side wall of a gate electrode by forming a gate electrode on an integrated circuit substrate and forming a thermal oxide layer on a side wall of the gate electrode using a thermal oxidation process. A silicide layer can be formed on the gate electrode after the formation of the thermal oxide layer.

Abstract: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Abstract: Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions therein. A gate insulator is provided on the first surface of the silicon well region and disposed between the source and drain regions and a gate electrode is provided on the gate insulator. A region of insulating material is disposed between a first surface of the drain region and the silicon well region. The region of insulating material extends toward but not to the source region. A source electrode is provided that contacts the source region. A drain electrode contacts the drain region and the region of insulating material.

Abstract: Fluorinated, diamond-like carbon (F-DLC) films are produced by a pulsed, glow-discharge plasma immersion ion processing procedure. The pulsed, glow-discharge plasma was generated at a pressure of 1 Pa from an acetylene (C2H2) and hexafluoroethane (C2F6) gas mixture, and the fluorinated, diamond-like carbon films were deposited on silicon <100>substrates. The film hardness and wear resistance were found to be strongly dependent on the fluorine content incorporated into the coatings. The hardness of the F-DLC films was found to decrease considerably when the fluorine content in the coatings reached about 20%. The contact angle of water on the F-DLC coatings was found to increase with increasing film fluorine content and to saturate at a level characteristic of polytetrafluoroethylene.

Abstract: A plasma-based method for the deposition of diamond-like carbon (DLC) coatings is described. The process uses a radio-frequency inductively coupled discharge to generate a plasma at relatively low gas pressures. The deposition process is environmentally friendly and scaleable to large areas, and components that have geometrically complicated surfaces can be processed. The method has been used to deposit adherent 100-400 nm thick DLC coatings on metals, glass, and polymers. These coatings are between three and four times harder than steel and are therefore scratch resistant, and transparent to visible light. Boron and silicon doping of the DLC coatings have produced coatings having improved optical properties and lower coating stress levels, but with slightly lower hardness.

Abstract: Fluorinated, diamond-like carbon (F-DLC) films are produced by a pulsed, glow-discharge plasma immersion ion processing procedure. The pulsed, glow-discharge plasma was generated at a pressure of 1 Pa from an acetylene (C2H2) and hexafluoroethane (C2F6) gas mixture, and the fluorinated, diamond-like carbon films were deposited on silicon <100>substrates. The film hardness and wear resistance were found to be strongly dependent on the fluorine content incorporated into the coatings. The hardness of the F-DLC films was found to decrease considerably when the fluorine content in the coatings reached about 20%. The contact angle of water on the F-DLC coatings was found to increase with increasing film fluorine content and to saturate at a level characteristic of polytetrafluoroethylene.