Abstract: A semiconductor device includes first IC dies disposed side-by-side, a second IC die overlapping and electrically coupled to the first IC dies, and first conductive features. Each first IC die includes first and second die connectors. A first pitch of the first die connectors is less than a second pitch of the second die connectors and is substantially equal to a third pitch of the third die connectors of the second IC die. The first conductive features are interposed between and electrically coupled to the first and third die connectors. Each first conductive feature includes at least a first conductive bump and at least a first conductive joint.

Abstract: A package device includes a top die having a top interconnect structure on a first surface of a transistor layer and a bottom interconnect structure on a second surface of the transistor layer. One of the top interconnect structure or the bottom interconnect structure is direct bonded onto a bottom die. The bottom interconnect structure includes a power rail which directly contacts transistor contacts that are directly contacting a transistor structure in the transistor layer.

Abstract: A package device for 3D stacking of integrated circuits includes a semiconductor substrate, and an interconnect structure on the semiconductor substrate. The interconnect structure is organized into a plurality of device regions, and the device has a first seal ring extending vertically through the interconnect structure in a first device region, and a second seal ring extending vertically through the interconnect structure in a second device region. The interconnect structure also includes a conductive line electrically connecting a metallization pattern within the first seal ring to a second metallization pattern within the second seal ring, wherein the first horizontally extending conductive line extends through the first seal ring and the second seal ring.

Abstract: Stacked semiconductor devices and methods of forming the same are provided. Contact pads are formed on a die. A passivation layer is blanket deposited over the contact pads. The passivation layer is subsequently patterned to form first openings, the first openings exposing the contact pads. A buffer layer is blanket deposited over the passivation layer and the contact pads. The buffer layer is subsequently patterned to form second openings, the second opening exposing a first set of the contact pads. First conductive pillars are formed in the second openings. Conductive lines are formed over the buffer layer simultaneously with the first conductive pillars, ends of the conductive lines terminating with the first conductive pillars. An external connector structure is formed over the first conductive pillars and the conductive lines, the first conductive pillars electrically coupling the contact pads to the external connector structure.

Abstract: In an embodiment, a package include an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds. The package further includes an encapsulant over the interposer and surrounding the integrated circuit die. The encapsulant is further disposed between the first insulating bonding layer and the second insulating bonding layer along a line perpendicular to a major surface of the first semiconductor substrate.

Abstract: In an embodiment, a package includes an integrated circuit die comprising a first insulating bonding layer and a first semiconductor substrate and an interposer comprising a second insulating bonding layer, a first seal ring, and a second semiconductor substrate. The second insulating bonding layer is directly bonded to the first insulating bonding layer with dielectric-to-dielectric bonds, and wherein the integrated circuit die overlaps the first seal ring. A sidewall of the integrated circuit die is exposed at an outer sidewall of the package.

Abstract: A method includes etching a portion of a wafer to form a first trench in a scribe line of the wafer, wherein the scribe line is between a first device die and a second device die of the wafer. After the etching, a top surface of the portion of wafer in the scribe line is underlying and exposed to the first trench, and the first trench is between opposing sidewalls of the wafer. A laser grooving process is then performed to form a second trench extending from the top surface further down into the wafer, and the second trench is laterally between the opposing sidewalls of the wafer. A die-saw process is then performed to saw the wafer. The die-saw process is performed from a bottom of the second trench, and the die-saw process results in the first device die to be separated from the second device die.

Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A semiconductor device and a forming method thereof are provided. The semiconductor device includes an integrated circuit (IC) die and an encapsulant. The IC die includes a semiconductor substrate and an interconnect structure connected to the semiconductor substrate, the semiconductor substrate includes a first ledge, and the interconnect structure includes a second ledge. The encapsulant extends along the first ledge of the first semiconductor substrate and the second ledge of the first interconnect structure.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor package includes a semiconductor die including an active surface and an electrical terminal on the active surface, and a redistribution circuitry disposed on the active surface of the semiconductor die and connected to the electrical terminal. A top surface of the redistribution circuitry includes a planar portion and a concave portion connected to the planar portion, the concave portion is directly over the electrical terminal, and a minimum distance measured from a lowest point of the concave portion to a virtual plane where the planar portion is located is equal to or smaller than 0.5 ?m.

Abstract: A method includes bonding a composite die on a redistribution structure. The composite die comprises a device die including a semiconductor substrate, a through-semiconductor via penetrating through the semiconductor substrate, a metal via at a surface of the device die, and a sacrificial carrier attached to the device die. The composite die is encapsulated in an encapsulant. A planarization process is performed on the composite die and the encapsulant, and the sacrificial carrier is removed to reveal the metal via. A conductive feature is formed to electrically couple to the metal via.

Abstract: A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.

Abstract: A method of manufacturing a semiconductor package includes forming an encapsulated semiconductor device and forming a redistribution structure over the encapsulated semiconductor device, where the encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. Forming the redistribution structure includes forming a first dielectric layer on the encapsulated semiconductor device, and forming a first redistribution circuit layer on the first dielectric layer by a plating process carried out at a current density of substantially 4˜6 amperes per square decimeter, where the first dielectric layer comprises a first via opening. An upper surface of the first redistribution circuit layer filling the first via opening is substantially coplanar with an upper surface of the rest of the first redistribution circuit layer.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: A method for forming a via in a semiconductor device and a semiconductor device including the via are disclosed. In an embodiment, the method may include bonding a first terminal and a second terminal of a first substrate to a third terminal and a fourth terminal of a second substrate; separating the first substrate to form a first component device and a second component device; forming a gap fill material over the first component device, the second component device, and the second substrate; forming a conductive via extending from a top surface of the gap fill material to a fifth terminal of the second substrate; and forming a top terminal over a top surface of the first component device, the top terminal connecting the first component device to the fifth terminal of the second substrate through the conductive via.