Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die bonded to the first integrated circuit die in a face-to-back manner; a dummy semiconductor feature adjacent the second integrated circuit die and bonded to the first integrated circuit die; a support substrate attached to the dummy semiconductor feature and the second integrated circuit die; and a passivation layer extending along a top surface of the support substrate, an outer sidewall of the dummy semiconductor feature, an outer sidewall of the first integrated circuit die, and a top surface of the first integrated circuit die.

Abstract: A method of forming an integrated circuit package includes following operations. A padding layer is formed on a portion of a carrier. A first semiconductor die is placed on the padding layer and a second semiconductor die is placed on the carrier. The first semiconductor die and the second semiconductor die are encapsulated with a first encapsulation layer. A first redistribution layer structure is formed over the first semiconductor die, the second semiconductor die and the first encapsulation layer. A third semiconductor die is placed on the first redistribution layer structure. The third semiconductor die is encapsulated with a second encapsulation layer. A second redistribution layer structure is formed over the third semiconductor die and the second encapsulation layer. The carrier is debonded. The padding layer is removed, and therefore, a recess is formed in the first encapsulation layer.

Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Abstract: A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.

Abstract: A semiconductor structure includes a semiconductor structure includes a semiconductor die, an insulating encapsulation, a passivation layer and conductive elements. The semiconductor die includes a sensor device and a semiconductor substrate with a first region and a second region adjacent to the first region, and the sensor device is embedded in the semiconductor substrate within the first region. The insulating encapsulation laterally encapsulates the semiconductor die and covers a sidewall of the semiconductor die. The passivation layer is located on the semiconductor die, wherein a recess penetrates through the passivation layer over the first region and is overlapped with the sensor device. The conductive elements are located on the passivation layer over the second region and are electrically connected to the semiconductor die, wherein the passivation layer is between the insulating encapsulation and the conductive elements.

Abstract: A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Abstract: A package structure including IPD and method of forming the same are provided. The package structure includes a die, an encapsulant laterally encapsulating the die, a first RDL structure disposed on the encapsulant and the die, an IPD disposed on the first RDL structure and an underfill layer. The IPD includes a substrate, a first connector on a first side of the substrate and electrically connected to the first RDL structure, a guard structure on a second side of the substrate opposite to the first side and laterally surrounding a connector region, and a second connector disposed within the connector region and electrically connected to a conductive via embedded in the substrate. The underfill layer is disposed to at least fill a space between the first side of the IPD and the first RDL structure. The underfill layer is separated from the connector region by the guard structure.

Abstract: An embodiment is a structure including a first die having an active surface with a first center point, a molding compound at least laterally encapsulating the first die, and a first redistribution layer (RDL) including metallization patterns extending over the first die and the molding compound. A first portion of the metallization patterns of the first RDL extending over a first portion of a boundary of the first die to the molding compound, the first portion of the metallization patterns not extending parallel to a first line, the first line extending from the first center point of the first die to the first portion of the boundary of the first die.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: A package structure includes a substrate, a semiconductor device and an adhesive layer. The semiconductor device is disposed on the substrate, wherein an angle ? is formed between one sidewall of the semiconductor device and one of sides of the substrate, 0°<?<90°. The adhesive layer surrounds the semiconductor device on the substrate and at least continuously disposed at two of the sides of the substrate, wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.

Abstract: A semiconductor device includes a first die extending through a molding compound layer, a first dummy die having a bottom embedded in the molding compound layer, wherein a height of the first die is greater than a height of the first dummy die, and an interconnect structure over the molding compound layer, wherein a first metal feature of the interconnect structure is electrically connected to the first die and a second metal feature of the interconnect structure is over the first dummy die and extends over a sidewall of the first dummy die.

Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.

Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.