Patents by Inventor Derrick Liu
Derrick Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240131326Abstract: A self-anchoring helical wire structure electrode for energy conduction to or from a tissue target in a body, made of at least one wire rope consisting of biocompatible and conductive wire, and enclosing a hollow core within an inner diameter and having a longitudinal axis, an outer diameter and two ends, being flexible for self-bending in any direction up to 180 degrees on said longitudinal axis, and secured by being capable of self-forming a bunching anchor wider than the insertion channel when injected while its dispenser is substantially stationary.Type: ApplicationFiled: May 17, 2021Publication date: April 25, 2024Inventors: Stephan NIEUWOUDT, Manfred FRANKE, Shaher AHMED, Derrick LIU, Amelia HOWE, Emily SZABO, Jennifer PECK
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Publication number: 20230338081Abstract: The invention is a system and method of minimally invasive treatment with wire structure electrodes dispensed without open cut downs or laparoscopy and using energy forms including radiofrequency, microwave, direct current, and high intensity focused ultrasound.Type: ApplicationFiled: May 19, 2021Publication date: October 26, 2023Inventors: Stephan NIEUWOUDT, Manfred FRANKE, David BOLUS, Derrick LIU, Emily SZABO, Shaher AHMAD, Aniruddha UPADHYE, Sean ZUCKERMANN, Craig WATSON, Andre SNELLINGS, Amelia HOWE
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Publication number: 20230024284Abstract: The invention is an injectable wire structure electrode which assimilates with surrounding tissues after injection, inducing in-growth of blood vessels, collagen and other tissue. Assimilation secures the electrode to the tissue without sutures and prevents relative motion which can lead to inflammation and scarring. Associated methods of manufacturing and injection are disclosed, as well as systems including a dermal multiplexer for power delivery.Type: ApplicationFiled: November 19, 2020Publication date: January 26, 2023Inventors: Manfred FRANKE, Shaher AHMAD, Stephan NIEUWOUDT, Amelia HOWE, Aniruddha UPADHYE, Emily SZABO, Derrick LIU, Sean ZUCKERMANN, Craig WATSON
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Patent number: 11282186Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: GrantFiled: March 18, 2020Date of Patent: March 22, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 11195969Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.Type: GrantFiled: August 3, 2018Date of Patent: December 7, 2021Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
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Patent number: 11056610Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.Type: GrantFiled: August 3, 2018Date of Patent: July 6, 2021Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
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Publication number: 20200219247Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: ApplicationFiled: March 18, 2020Publication date: July 9, 2020Inventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 10664966Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: GrantFiled: January 25, 2018Date of Patent: May 26, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 10615278Abstract: A semiconductor structure includes a stained fin, a gate upon the strain fin, and a spacer upon a sidewall of the gate and upon an end surface of the strained fin. The end surface of the strained fin is coplanar with a sidewall of the gate. The spacer limits relaxation of the strained fin.Type: GrantFiled: October 27, 2017Date of Patent: April 7, 2020Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung
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Publication number: 20190228519Abstract: An aspect of the invention includes reading a scale in image data representing an image of physical characteristics and resizing at least a portion of the image data to align with target image data representing a target image based at least in part on the scale to form resized image data representing one or more resized images. Noise reduction is applied to the resized image data to produce test image data representing one or more test images. A best fit analysis is performed on the test image data with respect to the target image data. Test image data having the best fit are stored with training image data representing classification training images indicative of one or more recognized features. An anomaly in unclassified image data representing an unclassified image is identified based at least in part on an anomaly detector as trained using the classification training images.Type: ApplicationFiled: January 25, 2018Publication date: July 25, 2019Inventors: Dechao Guo, Liying Jiang, Derrick Liu, Jingyun Zhang, Huimei Zhou
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Patent number: 10263098Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.Type: GrantFiled: October 19, 2017Date of Patent: April 16, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
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Patent number: 10224419Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.Type: GrantFiled: November 27, 2017Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
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Patent number: 10170477Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.Type: GrantFiled: November 6, 2015Date of Patent: January 1, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Gen Tsutsui, Reinaldo A. Vega, Koji Watanabe
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Patent number: 10170593Abstract: A method of forming an arrangement of long and short fins on a substrate, including forming a plurality of finFET devices having long fins on the substrate, where the long fins have a fin length in the range of about 180 nm to about 350 nm, and forming a plurality of finFET devices having short fins on the substrate, where the short fins have a fin length in the range of about 60 nm to about 140 nm, wherein at least one of the plurality of finFET devices having a long fin is adjacent to at least one of the plurality of finFET devices having a short fin.Type: GrantFiled: December 20, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Ruqiang Bao, Dechao Guo, Derrick Liu, Huimei Zhou
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Publication number: 20180358504Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.Type: ApplicationFiled: August 3, 2018Publication date: December 13, 2018Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
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Patent number: 10147839Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.Type: GrantFiled: August 18, 2015Date of Patent: December 4, 2018Assignee: International Business Machines CorporationInventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
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Patent number: 10147725Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.Type: GrantFiled: December 14, 2015Date of Patent: December 4, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ruqiang Bao, Gauri Karve, Derrick Liu, Robert R. Robison, Gen Tsutsui, Reinaldo A. Vega, Koji Watanabe
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Publication number: 20180342642Abstract: A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.Type: ApplicationFiled: August 3, 2018Publication date: November 29, 2018Applicant: International Business Machines CorporationInventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
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Patent number: 10121853Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.Type: GrantFiled: October 26, 2017Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg
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Patent number: 10121852Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.Type: GrantFiled: October 26, 2017Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg