Abstract: A method of making a semiconductor device comprises forming a first channel region comprising a first channel region material and a second channel region comprising a second channel region material; disposing a gate dielectric on the first channel region and second channel region; depositing a work function modifying material on the gate dielectric; disposing a mask over the work function modifying material deposited on the gate dielectric disposed on the first channel region; removing the work function modifying material from the unmasked gate dielectric disposed on the second channel region; removing the mask from the work function modifying material deposited on the gate dielectric disposed on the first channel region; forming a first gate electrode on the work function modifying material deposited on the first channel region and forming a second gate electrode on the gate dielectric disposed on the second channel region.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.

Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.

Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.

Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.

Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.

Abstract: Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.

Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.