Patents by Inventor Derrick Liu

Derrick Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9293221
    Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Derrick Liu, Chun-Chen Yeh
  • Patent number: 9287264
    Abstract: Embodiments of the present invention provide a method for epitaxially growing a FinFET. One method may include providing a semiconductor substrate including an insulator and an underlayer; forming a channel layer on the semiconductor substrate using epitaxial growth; etching a recess into the channel layer and epitaxially regrowing a portion on the channel layer; etching the channel layer and the underlayer to form fins; forming a gate structure and a set of spacers; etching a source drain region into the channel layer; and forming a source drain material in the source drain region.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kangguo Cheng, Eric C. T. Harley, Judson R. Holt, Gauri V. Karve, Yue Ke, Derrick Liu, Timothy J. McArdle, Shogo Mochizuki, Alexander Reznicek, Melissa A. Smith
  • Patent number: 9287000
    Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Derrick Liu, Chun-Chen Yeh
  • Publication number: 20150357512
    Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.
    Type: Application
    Filed: August 18, 2015
    Publication date: December 10, 2015
    Inventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette
  • Patent number: 8871549
    Abstract: Device structures, fabrication methods, and design structures for a biological and chemical sensor used to detect a property of a substance. The device structure includes a drain and a source of a field effect transistor formed at a frontside of a substrate. A sensing layer is formed at a backside of the substrate. The sensing layer is configured to receive the substance.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Derrick Liu
  • Patent number: 8679863
    Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Derrick Liu, Dale W. Martin, Gerd Pfeiffer
  • Publication number: 20130244348
    Abstract: Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. GAMBINO, Derrick LIU, Dale W. MARTIN, Gerd PFEIFFER
  • Publication number: 20130146335
    Abstract: Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Derrick Liu, Daniel S. Vanslette