Abstract: Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is placed on the target device. Optimizing placement of the system for routing is performed after placing the system. The system is routed after optimizing placement.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying a group of components associated with a critical signal in the system. A first copy and a second copy of the group of components are generated where the first copy is driven by a first signal at a first state and the second copy is driven by a second signal at a second state. The system is configured to select an output of one of the first copy and the second copy in response to the critical signal.

Abstract: A method for designing a system on a field programmable gate array (FPGA) includes using binary decision diagrams (BDDs) to perform functional decomposition on a design for the system after placement.

Abstract: A method for designing a system on a target device includes synthesizing the system. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system where a first descendant thread is spawned to run in parallel with an existing thread where the first descendant thread is executing a different optimization strategy than the existing thread but on a same netlist as the existing thread.

Abstract: A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.

Abstract: Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Where area savings are significant, smaller PLDs may be selected to implement a particular circuit. One aspect of the invention relates to methods for identifying sequential cones of logic that may be mapped into synchronous EMBs. After the sequential logic cones are identified for mapping into a synchronous EMB, the logic cone may be selected, expanded, restructured, and retimed, as necessary, to implement the mapping. Another aspect of the invention relates to techniques for handling architectural restrictions of synchronous EMBs, such as the inability to implement the asynchronous behavior of synchronous logic.

Abstract: Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condition of a set is found to be violated, the registers may be moved to another set having a different logic condition or removed completely. The registers remaining are potentially reducible. The reducibility of the registers is verified via Boolean analysis by verifying the logic conditions of a register set for each register. If a register does not pass verification, it then may be moved to a different set having a different logic condition or removed completely. The sets that pass verification are reducible.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes duplicating a plurality of components in response to slack values associated with connections to the components in placement locations.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes identifying registers on near-critical paths. The registers are moved to shorten lengths of one or more near-critical paths.

Abstract: Multiple optimization phases are combined to improve the performance and decrease the compilation time of user designs. An initial user design is compiled and analyzed to provide timing information. A two-pass optimization phase uses the timing information to optimize the user design. As the compilation process is repeated for the optimized user design, an incremental processing phase applies configuration information previously generated for the original user design to the corresponding portions of the optimized user design. Similarly, a selected one of a set of optimization algorithms can be applied to a modified user design, with the selection determined from an evaluation of the set of optimization algorithms on the unmodified user design. Additionally, external applications can perform one or more optimization phases on an original or modified user design.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes synthesizing a design for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. The design for the system is restructured after placement locations for the components are determined to improve timing for the system.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the components on the target device. Components to replicate are identified in response to criticality determined from the placement locations.

Abstract: A system and method improves the effectiveness of logic duplication optimizations by dynamically allocating the usage of logic duplicates. Duplicate atoms in the user design are identified. Atoms satisfying heuristics can also be duplicated and added to the user design. During placement, a duplicate-aware cost function is used to determine the location on the programmable device of atoms driven by a duplicate atom. The duplicate-aware cost function evaluates the suitability of a potential location of a driven atom with respect to a source atom and any duplicates of the source atom. Following placement of the atoms of the user design, a rewiring phase establishes a connection between each driven atom and one of the duplicated source atoms. The duplicate-aware cost function can be used to evaluate sets of duplicate source atoms to optimize the operating speed, power consumption, and/or routability of a user design.

Abstract: A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical design. A second design for the system is generated that includes a second netlist describing a second logical design. Changes made to the first design in the second design are identified. Placement is performed on the changes made to the first design on the second design.

Abstract: A programmable logic device has programmable phase-shifting circuitry. The phase-shifting circuitry is used to generate a set of skewed clock signals that is used to adjust the relative timing of device elements in a circuit synthesized in the programmable logic device. By suitably adjusting the relative timing of the device elements, the circuit critical path lengths are effectively reduced leading to improved circuit frequency performance. Algorithms are provided for establishing clock skew values that lead to improved circuit performance. The algorithms are incorporated in computer aided design tools to enable automatic optimization of circuit designs.