Patents by Inventor Deva Pattanayak
Deva Pattanayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453953Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: GrantFiled: December 21, 2016Date of Patent: October 22, 2019Assignee: VISHAY-SILICONIXInventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
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Patent number: 10340377Abstract: Edge termination for MOSFETs. In accordance with an embodiment of the present invention, a metal oxide semiconductor field effect transistor (MOSFET) includes a core region including a plurality of parallel core plates coupled to a source terminal of the MOSFET. The MOSFET also includes a termination region surrounding the core region comprising a plurality of separated floating termination segments configured to force breakdown into the core region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.Type: GrantFiled: May 15, 2017Date of Patent: July 2, 2019Assignee: Vishay-SiliconixInventor: Deva Pattanayak
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Patent number: 10283587Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.Type: GrantFiled: February 6, 2018Date of Patent: May 7, 2019Assignee: VISHAY-SILICONIXInventors: Deva Pattanayak, Olof Tornblad
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Publication number: 20180240869Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.Type: ApplicationFiled: February 6, 2018Publication date: August 23, 2018Inventors: Deva PATTANAYAK, Olof TORNBLAD
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Patent number: 10032901Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: April 5, 2016Date of Patent: July 24, 2018Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Patent number: 10026835Abstract: A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.Type: GrantFiled: June 25, 2010Date of Patent: July 17, 2018Assignee: Vishay-SiliconixInventors: Naveen Tipirneni, Deva Pattanayak
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Patent number: 9887266Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorus. The novel red Phosphorus doped substrate enables a desirable low drain-source resistance.Type: GrantFiled: February 11, 2008Date of Patent: February 6, 2018Assignee: Vishay-SiliconixInventors: The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen
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Patent number: 9887259Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.Type: GrantFiled: March 16, 2015Date of Patent: February 6, 2018Assignee: Vishay-SiliconixInventors: Deva Pattanayak, Olof Tornblad
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Patent number: 9882044Abstract: Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core super-junction region including a plurality of parallel core plates coupled to a source terminal of the super-junction MOSFET. The super-junction MOSFET also includes a termination region surrounding the core super-junction region comprising a plurality of separated floating termination segments configured to force breakdown into the core super-junction region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.Type: GrantFiled: August 19, 2015Date of Patent: January 30, 2018Assignee: Vishay-SiliconixInventor: Deva Pattanayak
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Patent number: 9831336Abstract: A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material.Type: GrantFiled: November 10, 2014Date of Patent: November 28, 2017Assignee: Vishay-SiliconixInventors: Zachary Lee, Deva Pattanayak
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Publication number: 20170250247Abstract: Edge termination for MOSFETs. In accordance with an embodiment of the present invention, a metal oxide semiconductor field effect transistor (MOSFET) includes a core region including a plurality of parallel core plates coupled to a source terminal of the MOSFET. The MOSFET also includes a termination region surrounding the core region comprising a plurality of separated floating termination segments configured to force breakdown into the core region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventor: Deva PATTANAYAK
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Publication number: 20170222022Abstract: A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column.Type: ApplicationFiled: April 13, 2017Publication date: August 3, 2017Inventors: Deva PATTANAYAK, Sandeep AGGARWAL
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Publication number: 20170104096Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Inventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
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Patent number: 9577089Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: GrantFiled: March 2, 2011Date of Patent: February 21, 2017Assignee: Vishay-SiliconixInventors: Kyle Terrill, Deva Pattanayak, Zhiyun Luo
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Publication number: 20170025527Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: April 5, 2016Publication date: January 26, 2017Inventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Patent number: 9508596Abstract: During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.Type: GrantFiled: June 20, 2014Date of Patent: November 29, 2016Assignee: Vishay-SiliconixInventors: Naveen Tipirneni, Deva Pattanayak
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Patent number: 9443974Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.Type: GrantFiled: August 27, 2009Date of Patent: September 13, 2016Assignee: Vishay-SiliconixInventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
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Patent number: 9437424Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on”resistance of the device.Type: GrantFiled: May 20, 2008Date of Patent: September 6, 2016Assignee: Vishay-SiliconixInventors: Deva Pattanayak, Kuo-In Chen, The-Tu Chau
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Patent number: 9431550Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: November 30, 2011Date of Patent: August 30, 2016Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
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Patent number: 9425043Abstract: High mobility P-channel power metal oxide semiconductor field effect transistors. In accordance with an embodiment of the present invention, a power MOSFET is fabricated such that the holes flow in an inversion/accumulation channel, which is along the (110) crystalline plane, or equivalents, and the current flow is in the [110] direction, or equivalents, when a negative potential is applied to the gate with respect to the source. The enhanced channel mobility of holes leads to a reduction of the channel portion of the on-state resistance, thereby advantageously reducing total “on” resistance of the device.Type: GrantFiled: December 22, 2006Date of Patent: August 23, 2016Assignee: Vishay-SiliconixInventors: Deva Pattanayak, Kuo-In Chen, The-Tu Chau