Patents by Inventor Deva Pattanayak
Deva Pattanayak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9425306Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.Type: GrantFiled: August 27, 2009Date of Patent: August 23, 2016Assignee: Vishay-SiliconixInventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
-
Patent number: 9306056Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: October 30, 2009Date of Patent: April 5, 2016Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
-
Publication number: 20160056281Abstract: Edge termination for super-junction MOSFETs. In accordance with an embodiment of the present invention, a super-junction metal oxide semiconductor field effect transistor (MOSFET) includes a core super-junction region including a plurality of parallel core plates coupled to a source terminal of the super-junction MOSFET. The super-junction MOSFET also includes a termination region surrounding the core super-junction region comprising a plurality of separated floating termination segments configured to force breakdown into the core super-junction region and not in the termination region. Each termination segment has a length dimension less than a length dimension of the core plates.Type: ApplicationFiled: August 19, 2015Publication date: February 25, 2016Inventor: Deva PATTANAYAK
-
Publication number: 20150372132Abstract: A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column.Type: ApplicationFiled: March 16, 2015Publication date: December 24, 2015Inventors: Deva PATTANAYAK, Sandeep AGGARWAL
-
Publication number: 20150372078Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.Type: ApplicationFiled: March 16, 2015Publication date: December 24, 2015Inventors: Deva PATTANAYAK, Olof TORNBLAD
-
Publication number: 20150372077Abstract: During fabrication, a second oxide layer is disposed over a first region and a second region of a structure. The second region includes a first oxide layer between the second oxide layer and an epitaxial layer. The first region corresponds to an active region of a metal-insulator-semiconductor field effect transistor (MISFET), and a first-type dopant source region, a second-type dopant body region, and a second-type dopant implant region are formed in the first region. The second region corresponds to a termination region of the MISFET. A mask is formed over the second region, and parts of the second oxide layer and the first oxide layer that are exposed through the gaps are removed, thereby exposing the epitaxial layer. Second-type dopant is deposited into the epitaxial layer through the resultant openings in the first and second oxide layers, thereby forming field rings for the MISFET.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Naveen TIPIRNENI, Deva PATTANAYAK
-
Publication number: 20150061000Abstract: A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material.Type: ApplicationFiled: November 10, 2014Publication date: March 5, 2015Inventors: Zachary Lee, Deva Pattanayak
-
Patent number: 8883595Abstract: A process for forming a short channel trench MOSFET. The process includes forming a first implant at the bottom of a trench that is formed in the body of the trench MOSFET and forming a second or angled implant that is tilted in its orientation and directed perpendicular to the trench that is formed in the body of the trench MOSFET. The second implant is adjusted so that it does not reach the bottom of the trench. In one embodiment the angled implant is n-type material.Type: GrantFiled: February 23, 2007Date of Patent: November 11, 2014Assignee: Vishay-SiliconixInventors: Zachary Lee, Deva Pattanayak
-
Patent number: 8409954Abstract: Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.Type: GrantFiled: March 21, 2006Date of Patent: April 2, 2013Assignee: Vishay-SilconixInventors: The-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen
-
Patent number: 8183629Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.Type: GrantFiled: March 18, 2008Date of Patent: May 22, 2012Assignee: Vishay-SiliconixInventors: Deva Pattanayak, Jason (Jianhai) Qi, Yuming Bai, Kam-Hong Lui, Ronald Wong
-
Publication number: 20120068178Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: ApplicationFiled: November 30, 2011Publication date: March 22, 2012Applicant: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
-
Patent number: 8072013Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: November 3, 2009Date of Patent: December 6, 2011Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
-
Publication number: 20110254084Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.Type: ApplicationFiled: March 2, 2011Publication date: October 20, 2011Applicant: VISHAY-SILICONIXInventors: Kyle Terrill, Yuming Bai, Deva Pattanayak, Zhiyun Luo
-
Publication number: 20110101525Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: VISHAY-SILICONIXInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
-
Publication number: 20110049614Abstract: In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Applicant: VISHAY-SILICONIXInventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
-
Publication number: 20110053326Abstract: Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In an n-channel device, a gate element for the FET is advantageously situated over the column of p-type dopant; and in a p-channel device, a gate element for the FET is advantageously situated over the column of n-type dopant.Type: ApplicationFiled: August 27, 2009Publication date: March 3, 2011Applicant: VISHAY-SILICONIXInventors: Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo-In Chen, The-Tu Chau, Sharon Shi, Qufei Chen
-
Publication number: 20100200893Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.Type: ApplicationFiled: April 1, 2010Publication date: August 12, 2010Inventors: Vic TEMPLE, Forrest HOLROYD, Sabih AL-MARAYATI, Deva PATTANAYAK
-
Patent number: 7692211Abstract: A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces.Type: GrantFiled: October 2, 2001Date of Patent: April 6, 2010Assignee: Silicon Power CorporationInventors: Vic Temple, Forrest Holroyd, Sabih Al-Marayati, Deva Pattanayak
-
Patent number: 7612431Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: January 17, 2008Date of Patent: November 3, 2009Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak
-
Patent number: 7544545Abstract: Embodiments of the present invention include a method of manufacturing a trench polysilicon diode. The method includes forming a N?(P?) type epitaxial region on a N+(P+) type substrate and forming a trench in the N?(P?) type epitaxial region. The method further includes forming a insulating layer in the trench and filling the trench with polysilicon forming a top surface of the trench. The method further includes forming P+(N+) type doped polysilicon region and N+(P+) type doped polysilicon region in the trench and forming a diode in the trench wherein a portion of the diode is lower than the top surface of the trench.Type: GrantFiled: December 28, 2005Date of Patent: June 9, 2009Assignee: Vishay-SiliconixInventors: Qufei Chen, Robert Xu, Kyle Terrill, Deva Pattanayak