Abstract: Shell-structured particles for sunscreen applications are provided herein. A method includes selecting one or more particles to serve as a core material in a sunscreen composition, wherein each of the one or more particles comprises a band gap within a predetermined range, and wherein said selecting is based on a desired absorption spectrum of the sunscreen composition; coating the one or more particles with at least one layer of zinc oxide.

Abstract: Shell-structured particles for sunscreen applications are provided herein. A method includes selecting one or more particles to serve as a core material in a sunscreen composition, wherein each of the one or more particles comprises a band gap within a predetermined range, and wherein said selecting is based on a desired absorption spectrum of the sunscreen composition; coating the one or more particles with at least one layer of zinc oxide. A composition includes selecting one or more particles to serve as a coating layer in a sunscreen composition, wherein each of the one or more particles comprises a band gap within a predetermined range, and wherein said selecting is based on a desired absorption spectrum of the sunscreen composition; and coating one or more zinc oxide particles with the one or more selected particles.

Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.

Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

Abstract: A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.

Abstract: Aspects of the present disclosure include a semiconductor structure comprising a gate layer with an associated gate dielectric thereon, and a region comprising at least one fin structure in contact with the gate layer, wherein the fin structure includes at least two distinct materials, and wherein one of the two distinct materials is a Zn based material.

Abstract: Aspects of the present disclosure include a structure and method of making a semiconductor device. The method includes: providing a gate structure, wherein the gate structure comprises a gate dielectric in contact with a III-V fin structure, depositing a spacer material over the gate structure and the fin structure, recessing the spacer material to form at least one sidewall spacer in contact with the gate, recessing a portion of the fin structure to create a recessed III-V fin structure, wherein the recessing of a portion of the fin structure creates an opening between at least two portions of the deposited spacer material; and depositing a Zn based material over i) the spacer material, ii) the recessed at least one fin structure and iii) the gate structure.

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

Abstract: Aspects of the present disclosure include a structure and method of making a semiconductor device. The method includes: providing a gate structure, wherein the gate structure comprises a gate dielectric in contact with a III-V fin structure, depositing a spacer material over the gate structure and the fin structure, recessing the spacer material to form at least one sidewall spacer in contact with the gate, recessing a portion of the fin structure to create a recessed III-V fin structure, wherein the recessing of a portion of the fin structure creates an opening between at least two portions of the deposited spacer material; and depositing a Zn based material over i) the spacer material, ii) the recessed at least one fin structure and iii) the gate structure.

Abstract: A semiconductor structure for optical power conversion and a method of forming the semiconductor structure are provided. In an aspect, the method may include removing a first portion of the semiconductor structure from a first region, wherein the semiconductor structure comprises a layered photovoltaic structure on a silicon-on-insulator structure. A second portion of the semiconductor structure may be removed from a second region, wherein the second region is located adjacent to the first region, and wherein an insulator layer of the silicon-on-insulator structure is exposed by the removed second portion. A passivation layer pattern may be formed over the semiconductor structure. Electrodes may be formed on portions of the surfaces of the semiconductor structure that are uncovered by the passivation layer.

Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.

Abstract: Nitride-based nanoparticles for use in sunscreen applications provided herein. A method includes selecting one or more nitride-based nanoparticles to serve as a core material in a sunscreen composition, wherein said selecting is based on a desired absorption spectrum of the sunscreen composition, and adjusting an amount of at least one element present within the nitride-based nanoparticles to achieve one or more user-defined optical characteristics with respect to the core material in the sunscreen composition. A composition includes one or more nitride-based nanoparticles constituting a core material in a sunscreen composition, wherein said nitride-based nanoparticles are selected based on a desired absorption spectrum of the sunscreen composition, and wherein an amount of at least one element present within the nitride-based nanoparticles is adjustable to achieve one or more user-defined optical characteristics.

Abstract: A computing process and product produced by the process comprises applying a write-erase cycle to a battery article of manufacture by applying a voltage controlled current source write signal to the battery in order to charge the battery, and subsequently erasing the signal by discharging the battery, where the battery comprises a plurality of components operatively associated with one another, the plurality of components comprising an electrode comprised of a material that can attract cations and repel cations in a charging and discharging process, an electrolyte operatively associated with the electrode, the electrolyte comprised of the cations the article of manufacture also including a component comprising at least one barrier component positioned between the electrolyte and the electrode, the barrier component comprised of a material and having a structure that substantially prevents the cations from combining with the electrode, but allows the cations to travel toward or away from the electrode in the c

Abstract: A battery article of manufacture comprises a plurality of components operatively associated with one another, the plurality of components comprising an electrode comprised of a material that can take up ions and discharge ions in a charging and discharging process, an electrolyte comprised of the ions, the article of manufacture also including a component comprising at least one barrier positioned between the electrolyte and the electrode, the barrier comprised of a material that substantially prevents the ions from combining with the electrode and having a structure that substantially prevents the ions from combining with the electrode, but allows the ions to travel toward or away from the electrode in the charging or discharging process.

Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

Abstract: A high speed thin film two terminal resistive memory article of manufacture comprises a chargeable and dischargeable variable resistance thin film battery having a plurality of layers operatively associated with one another, the plurality of layers comprising in sequence, a cathode-side conductive layer, a cathode layer comprised of a material that can take up cations and discharge cations in a charging and discharging process, an electrolyte layer comprising the cations, a barrier layer, an anode layer, and an optional anode-side conductive layer, the barrier layer comprised of a material that substantially prevents the cations from combining with the anode layer.

Abstract: An approach to deposit, by a self-aligning process, a layer of graphene on a gate formed on a dielectric layer on a semiconductor substrate where the gate includes a metal catalyst material. The approach includes removing a portion of the dielectric layer and a portion of the semiconductor substrate not under the gate and depositing, by a self-aligning atomic layer deposition process, a layer of a material capable of creating a source and a drain in a semiconductor device on exposed surfaces of the semiconductor substrate and the dielectric layer. The approach includes removing the layer of graphene from the gate, and, then removing a portion of the layer of the material capable of creating the source and the drain in the semiconductor device.