Patents by Inventor Dexter Chun

Dexter Chun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190176838
    Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Mohammad Reza KAKOEE, Rahul Gulati, Eric Mahurin, Suresh Kumar Venkumahanti, Dexter Chun
  • Patent number: 10310757
    Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 4, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Larry Bassel, Thomas Zeng, Dexter Chun
  • Patent number: 10296069
    Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 21, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Stewart, Dexter Chun
  • Publication number: 20190065087
    Abstract: Systems, methods, and computer programs are disclosed for reducing memory power consumption. An exemplary method comprises configuring a power saving memory balloon associated with a volatile memory. Memory allocations are steered to the power saving memory balloon. In response to initiating a memory power saving mode, data is migrated from the power saving memory balloon. A power saving feature is executed on the power saving memory balloon while in the memory power saving mode.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: YANRU LI, Larry Bassel, Thomas Zeng, Dexter Chun
  • Publication number: 20190065752
    Abstract: System and methods for booting a system-on-chip (SOC) in an enhanced memory mode are described herein. In one aspect, an enhanced memory mode indicator may be read to create a trusted channel to a non-volatile random-access memory (NVRAM). The NVRAM may be logically connected to the SOC. In an aspect, the NVRAM may be secured prior to the creation of the trusted channel. Once the secure channel to NVRAM has been created, the SOC may operate in an enhanced memory mode. Prior to the SOC powering down, the system may store an indicator operable to enable a subsequent boot of the SOC in the power saving mode. The SOC may be operable to switch between the power saving mode and a normal mode depending on the operational requirements of the portable computing device in which the SOC is implemented.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 28, 2019
    Inventors: Yanru Li, Azzedine Touzni, Dexter Chun
  • Publication number: 20190006001
    Abstract: Systems and methods are disclosed for error correction control (ECC) for a refreshable memory device coupled to a system on a chip SoC. The memory device including a parity region and a user data region. A method includes determining with the SoC a first refresh rate for the user data region of the memory device and a second refresh rate for the parity region of the memory device, where the second refresh rate is different than the first refresh rate. Parity data is generated for a write operation of a user payload data (UPD) to the user data region of the memory device. The user data region of the memory device is refreshed at the first refresh rate and the parity region is refreshed at the second refresh rate.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 3, 2019
    Inventors: DEXTER CHUN, Yanru Li
  • Publication number: 20180373314
    Abstract: Systems, methods, and computer programs are disclosed for reducing dynamic random access memory (DRAM) power consumption within a selected voltage frequency/bin. One embodiment is a method comprising receiving a selected voltage/frequency bin for operating a memory bus electrically coupling a memory controller to a dynamic random access memory (DRAM). The method monitors a bandwidth of the memory bus while operating at the selected voltage/frequency bin. The method frequency switches a clock for the memory bus, based on the monitored bandwidth, between a plurality of predefined frequencies within the selected voltage/frequency bin to maintain a target bandwidth.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 27, 2018
    Inventors: RICHARD STEWART, DEXTER CHUN
  • Publication number: 20180335828
    Abstract: Systems and methods are disclosed for reducing double data rate (DDR) memory power consumption via device-specific customization of DDR interface parameters. One embodiment comprises a method for minimizing double data rate (DDR) power consumption. The method selects one of a plurality of operating points for a DDR interface electrically coupling a DDR memory to a memory controller residing on a system on chip (SoC). The memory controller executes a memory test via the DDR interface at the selected operating point. During the execution of the memory test at the selected operating point, the method determines an optimal value of a setting for one or more DDR interface parameters associated with the DDR interface that minimizes memory power consumption and maintains a predetermined DDR eye margin.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 22, 2018
    Inventors: DEXTER CHUN, RICHARD STEWART
  • Publication number: 20180286473
    Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.
    Type: Application
    Filed: March 29, 2017
    Publication date: October 4, 2018
    Inventors: DEXTER CHUN, YANRU LI
  • Patent number: 10090040
    Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 2, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dexter Chun, Yanru Li
  • Publication number: 20180260320
    Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 13, 2018
    Inventors: Yanru Li, Dexter Chun, William Kimberly
  • Publication number: 20180197594
    Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.
    Type: Application
    Filed: January 6, 2017
    Publication date: July 12, 2018
    Inventors: Yanru Li, Dexter Chun, Jungwon Suh
  • Publication number: 20180189195
    Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: DEXTER CHUN, YANRU LI
  • Publication number: 20180052785
    Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.
    Type: Application
    Filed: August 22, 2016
    Publication date: February 22, 2018
    Inventors: Jungwon Suh, Dexter Chun, Haw-Jing Lo
  • Patent number: 9864536
    Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: January 9, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Dexter Chun, Haw-Jing Lo
  • Publication number: 20170371593
    Abstract: Systems, methods, and computer programs are disclosed for selectively compressing/decompressing flash storage data. An embodiment of a system comprises a compression/decompression component, a flash memory device, a flash controller in communication with the flash memory device, and a storage driver in communication with the compression/decompression component and the flash controller. The storage driver is configured to selectively control compression and decompression of data stored in the flash memory device, via the compression/decompression component, according to a storage usage collar comprising an upper usage threshold and a lower usage threshold.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: YANRU LI, DEXTER CHUN
  • Publication number: 20170371595
    Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: SUBRATO KUMAR DE, DEXTER CHUN, YANRU LI
  • Patent number: 9779798
    Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 3, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Yanru Li, Dexter Chun, Jungwon Suh, Alexander Gantman
  • Publication number: 20170220268
    Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.
    Type: Application
    Filed: March 22, 2016
    Publication date: August 3, 2017
    Inventors: VALMICK GUHA, Narasimhan Agaram, Ranjith Kumar Narahari, Dexter Chun
  • Patent number: 9612648
    Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM INCORPORATED
    Inventors: Dexter Chun, Yanru Li, Alex Tu, Haw-Jing Lo