Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

Abstract: Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT?PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Abstract: A base station controller system comprises a high data rate distributed switching fabric providing flexible access to call processing resource pools. The arrangement permits a system controller to selectively assign specific resources depending on call type based on configuring the distributed switching fabric. The transport links comprising the distributed switching fabric provide redundant access to each of the resource pools, greatly reducing the portion of overall call processing capability lost with a single failure. Preferably, the distributed switching fabric comprises a central ATM switch and a number of distributed ATM switches interconnecting the resource pools to the central switching resource. The system may adopt a rack arrangement wherein a processing subrack includes the mix of different processing resources necessary to support substantially all call flow processing for one or more types of calls.

Abstract: Techniques to securely boot up an electronics device (e.g., a cellular phone) from an external storage device are described. Secure data (e.g., a hash digest, a signature, a cryptographic key, and so on) is initially retrieved from a non-writable area of an external memory device (e.g., an one-time programmable (OTP) area of a NAND Flash device). A first program (e.g., a boot program) is retrieved from a writable or main area of the external memory device and authenticated based on the secure data. The first program is enabled for execution if authenticated. A second program may be retrieved from the main area of the external memory device and authenticated based on the secure data. The second program is enabled for execution if authenticated. Additional programs may be retrieved and authenticated. Each program may be authenticated using a secure hash function, a digital signature, and/or some other cryptographic technique.

Abstract: A timing network for a wireless communication network includes first and second Timing Unit Board (TUB) and processor boards for processing speech channels of the radio network, each processor board having a local timer that is slave to “PSTN time” from a Public Switch Telephone Network (PSTN). The first and second TUB each alternately transmits a timing cell containing time information to each processor board over a transport network. Each processor board realigns its local timer with the time information contained in a received timing cell whenever its local timer drifts from the time information contained in the received timing cell by a predetermined time offset. When one of the TUBs fails to transmit timing cells to the processor boards or transmits timing cells containing erroneous time information, the processor boards rely on the remaining TUB for timing cells to realign their local timers.

Abstract: Techniques for quickly and reliably accessing a memory device (e.g., a NAND Flash memory) with adaptive interface timing are described. For memory access with adaptive interface timing, the NAND Flash memory is accessed at an initial memory access rate, which may be the rate predicted to achieve reliable memory access. Error correction coding (ECC), which is often employed for NAND Flash memory, is then used to ensure reliable access of the NAND Flash. For a read operation, one page of data is read at a time from the NAND Flash memory, and the ECC determines whether the page read from the NAND Flash memory contains any errors. If errors are encountered, then a slower memory access rate is selected, and the page with error is read again from the NAND Flash memory at the new rate. The techniques may be used to write data to the NAND Flash memory.

Abstract: Systems and techniques are disclosed relating to calibrating an integrated circuit to an electronic component. The systems and techniques include an integrated circuit configured to generate a system clock and an external clock having a programmable delay from the system clock. The integrated circuit may also be configured to provide the external clock to the electronic component to support communications therewith, communicate with the electronic component, and calibrate the external clock delay as a function of the communications.

Abstract: A Base Station Controller (BSC) that reduces the occurrence of audible noise in a Code Division Multiple Access (CDMA) radio network is provided. The BSC according to one embodiment of the present invention comprises a Media Stream Board (MSB) for compressing groups of 160 PCM speech samples from a Public Switch Telephone Network (PSTN) into vocoded frames, and a Special Purpose Board (SPB) for reformatting the vocoded frames from the MSB into over-the-air CDMA vocoded frames. The MSB and SPB each have a local timer that is slave to “PSTN time”. The BSC further comprises a Timing Unit Board (TUB) connected to a GPS receiver. The TUB receives “GPS time” from the GPS receiver. The TUB generates timing cells, each containing time-of-day information according to “GPS time”. The TUB distributes the timing cells to the MSB and the SPB over an Asynchronous Transfer Mode (ATM) network. The MSB and SPB use the received timing cells to compare their local timer, which tracks “PSTN time”, to “GPS time”.

Abstract: A base station controller system comprises a high data rate distributed switching fabric providing flexible access to call processing resource pools. The arrangement permits a system controller to selectively assign specific resources depending on call type based on configuring the distributed switching fabric. The transport links comprising the distributed switching fabric provide redundant access to each of the resource pools, greatly reducing the portion of overall call processing capability lost with a single failure. Preferably, the distributed switching fabric comprises a central ATM switch and a number of distributed ATM switches interconnecting the resource pools to the central switching resource. The system may adopt a rack arrangement wherein a processing subrack includes the mix of different processing resources necessary to support substantially all call flow processing for one or more types of calls.

Abstract: A timing network for a wireless communication network includes first and second Timing Unit Board (TUB) and processor boards for processing speech channels of the radio network, each processor board having a local timer that is slave to “PSTN time” from a Public Switch Telephone Network (PSTN). The first and second TUB each alternately transmits a timing cell containing time information to each processor board over a transport network. Each processor board realigns its local timer with the time information contained in a received timing cell whenever its local timer drifts from the time information contained in the received timing cell by a predetermined time offset. When one of the TUBs fails to transmit timing cells to the processor boards or transmits timing cells containing erroneous time information, the processor boards rely on the remaining TUB for timing cells to realign their local timers.