Abstract: Systems and methods are disclosed for reducing memory power consumption via pre-filled dynamic random access memory (DRAM) values. One embodiment is a method for providing DRAM values. A fill request is received from an executing program to fill an allocated portion of the DRAM with a predetermined pattern of values. The predetermined pattern of values is stored in a fill value memory residing in the DRAM. A fill command is sent to the DRAM. In response to the fill command, a plurality of sense amp latches are connected to the fill value memory to update the corresponding sense amp latch bits with the predetermined pattern of values stored in the fill value memory.

Abstract: Systems, methods, and computer programs are disclosed for providing power-efficient file system operation to a non-volatile block memory. An exemplary embodiment of a system comprises a non-volatile block memory having a file system, a dynamic random access memory (DRAM), and a system on chip (SoC). The SoC comprises a central processing unit (CPU), one or more non-core processors, a DRAM controller, a data interface coupled to an off-chip processor, and a multi-host storage controller. The CPU allocates a storage buffer in the non-volatile block memory. The multi-host storage controller comprises a virtualized client interface for providing the non-core and off-chip processors with direct read/write file system access using the allocated storage buffer while the CPU and the DRAM are in a low power state.

Abstract: Systems, methods, and computer programs are disclosed for providing coincident memory bank access. One embodiment is a memory device comprising a first bank, a second bank, a first bank resource, and a second bank resource. The first bank has a first set of bitlines for accessing a first set of rows in a first memory cell array. The second bank has a second set of bitlines for accessing a second set of rows in a second memory cell array. The first bank resource and the second bank resource are selectively connected to the first set of bitlines or the second set of bitlines via a cross-connect switch.

Abstract: Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

Abstract: Systems, methods, and computer programs are disclosed for scheduling decompression of an application from flash storage. One embodiment of a system comprises a flash memory device and a preemptive decompression scheduler component. The preemptive decompression scheduler component comprises logic configured to generate and store metadata defining one or more dependent objects associated with the compressed application in response to an application installer component installing a compressed application to the flash memory device. In response to a launch of the compressed application by an application launcher component, the preemptive decompression scheduler component determines from the stored metadata the one or more dependent objects associated with the compressed application to be launched. The preemptive decompression scheduler component preemptively schedules decompression of the one or more dependent objects based on the stored metadata.

Abstract: Systems, methods, and computer programs are disclosed for selectively compressing/decompressing flash storage data. An embodiment of a system comprises a compression/decompression component, a flash memory device, a flash controller in communication with the flash memory device, and a storage driver in communication with the compression/decompression component and the flash controller. The storage driver is configured to selectively control compression and decompression of data stored in the flash memory device, via the compression/decompression component, according to a storage usage collar comprising an upper usage threshold and a lower usage threshold.

Abstract: Systems, methods, and computer programs for providing row tamper protection in a multi-bank memory cell array. One method comprises monitoring row activation activity for each of a plurality of banks in a multi-bank memory cell array. In response to monitoring the row activation activity, a row activation counter table is stored in a memory. The row activation counter table comprises a plurality of row address entries, each row address entry having a corresponding row activation counter. In response to detecting one of the plurality of row activation counters has exceeded a threshold indicating suspicious row tampering, the corresponding row address entry associated with the row activation counter exceeding the threshold is determined. A refresh operation is performed on one or more rows adjacent to the row address having the row activation counter exceeding the threshold.

Abstract: Systems and methods are disclosed for ensuring a target lifetime of a memory device coupled to an SoC of a computing device, the SoC including a central processing unit (CPU) executing an operating system (O/S). A DRAM is coupled to the SoC, and the memory device is configured to receive page swaps from the DRAM. A swap lifetime controller (SLC) in communication with the O/S is configured to determine a number of page swaps for the memory device during a time interval. A learning prediction system (LPS) in communication with the SLC is configured to determine a target number of page swaps (target_swap) to the memory device and a remaining life of the memory device (remaining_life_of_device). The SLC determines the number of page swaps based on the target_swap and remaining_life_of_device.

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract: Methods and devices for refreshing a dynamic memory device, (e.g., DRAM) to eliminate unnecessary page refresh operations. A value in a lookup table for the page may indicate whether valid data including all zeros is present in the page. When the page includes valid data of all zeros, the lookup table value may be set so that refresh, memory read, write and clear accesses of the page may be inhibited and a valid value may be returned. A second lookup table may contain a second value indicating whether a page has been accessed by a page read or write during the page refresh interval. A page refresh, by issuing an ACT?PRE command pair, and a page address may be performed according to the page refresh interval when the second value indicates that page access has not occurred.

Abstract: Various embodiments of methods and systems for deep coalescing memory management (“DCMM”) in a portable computing device (“PCD”) are disclosed. Because multiple active multimedia (“MM”) clients running on the PCD may generate a random stream of mixed read and write requests associated with data stored at non-contiguous addresses in a double data rate (“DDR”) memory component, DCMM solutions triage the requests into dedicated deep coalescing (“DC”) cache buffers, sequentially ordering the requests and/or the DC buffers based on associated addresses for the data in the DDR, to optimize read and write transactions from and to the DDR memory component in blocks of contiguous data addresses.

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract: A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state.

Abstract: Systems and methods are disclosed for providing multi-user power saving codebook optimization. One such method comprises: generating a unique codebook for a plurality of computing devices, each unique codebook configured for encoding memory data in the corresponding computing device; providing the unique codebooks to the corresponding computing devices via a communications networks; receiving compression statistics from one or more of the computing devices via the communications network, the compression statistics related to the corresponding unique codebook; and generating an optimized codebook for at least one of the computing devices based on the received compression statistics.

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.