Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

Abstract: Various embodiments of methods and systems for a modem-directed application processor boot flow in a portable computing device (“PCD”) are disclosed. An exemplary method includes an application processor that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine and/or crypto engine. That is, the application processor may “sleep” while the DMA engine and/or crypto engine process workloads in response to instructions they received from the application processor.

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.

Abstract: Disclosed are techniques for generating a parity check matrix representing an error correcting code (ECC) for protecting a plurality of bits of a message. In an aspect, a method includes initializing a matrix M to store selected three-bit codes, selecting a first three-bit code from a set L of three-bit combinations of a number of bits n of the ECC that minimizes a sum of squared row weights of each row of the matrix M, comparing the first three-bit code with each of a plurality of error syndromes, and calculating, based on no comparison of the first three-bit code with each of the plurality of error syndromes, new error syndromes and storing the new error syndromes, wherein the new error syndromes are calculated by comparing the first three-bit code with each three-bit code in the matrix M, and storing the first three-bit code in the matrix M.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.

Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of controlling a memory of a computing device by an adaptive memory controller. The method includes collecting usage data from the computing device over a first bin, wherein the first bin is associated with a first weight, wherein the first weight is indicative of one or more of a first partial array self-refresh (PASR) setting a first partial array auto refresh (PAAR) setting and a first deep power down (DPD) setting. The method further includes associating the collected data with a second weight, adapting the first bin based on the second weight, wherein the second weight is indicative of one or more of a second PASR, PAAR, and DPD setting. The method further includes controlling the memory during the next first bin based on the second weight.

Abstract: In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

Abstract: Pipelined logic latency in a memory system operating at a reduced frequency may be compensated for. Pipelined logic may be controlled using at least first and second clock signals. All registers of the pipelined logic may be controlled using the first clock signal when the memory system is operating at a higher frequency. However, when the memory system is operating at a reduced frequency, one or more registers may be controlled using the first clock signal, and one or more other registers may be controlled using the second clock signal.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: This disclosure relates to allocating memory resources of a computing device comprising non-volatile random access memory (NVRAM) and dynamic random access memory (DRAM). An exemplary method is performed for every independently executable component of an application and includes determining attributes of the component. The method also includes associating the component with a memory profile of a plurality of memory profiles based on the attributes, wherein each memory profile of the plurality of memory profiles specifies a number of banks of the NVRAM and a number of banks of the DRAM. The method also includes causing the computing device to generate an assignment of the component to banks of the NVRAM and DRAM based on the memory profile associated with the component so the computing device can execute the component using the banks of the NVRAM and DRAM based on the assignment.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.