Abstract: A clock is distributed to a processor-side base mode clocked transceiver and to a memory-side base mode clocked transceiver, interfacing respective ends of a data lane between a processor and the memory, for duplex communicating over the data lane. Concurrent with the duplex communicating, a bandwidth mode switches between a base bandwidth mode and a scale-up mode. The scale-up mode enables scale-up clock lines that distribute the clock to a processor-side scale-up transceiver and to a memory-side scale-up transceiver, interfacing respective ends of a scale-up data lane between the processor and the memory, for additional duplex communicating over the scale-up data lane. The base bandwidth mode disables the scale-up clock lines, which disables communicating over the scale-up data lane.

Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device comprises an input/output (I/O) interface, and an I/O voltage controller. The I/O voltage controller is configured to determine a frequency or temperature of the I/O interface, and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing a signal to each of a plurality of processors on a system on chip (SoC) for scheduling the maintenance event; each of the plurality of processors independently generating in response to the signal a corresponding schedule notification for the maintenance event; and the memory controller determining when to execute the maintenance event in response to receiving one or more of the schedule notifications generated by the plurality of processors and based on a processor priority scheme.

Abstract: Systems, methods, and computer programs are disclosed for scheduling volatile memory maintenance events. One embodiment is a method comprising: a memory controller determining a time-of-service (ToS) window for executing a maintenance event for a volatile memory device coupled to the memory controller via a memory data interface; the memory controller providing an interrupt signal to a processing unit; determining a priority for the maintenance event; and scheduling the maintenance event according to the priority.

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract: A memory module comprising a non-volatile cell array and a re-mapper. A page map table is stored in the non-volatile cell array, and includes mappings of old page addresses to new page addresses. The re-mapper is configured to direct memory operations referencing an old page address to the new page address that the old page address is mapped to. The mappings are created when a memory cell is determined to be in a failure state.

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture.

Abstract: Systems, methods, and computer programs are disclosed for allocating memory in a portable computing device having a non-uniform memory architecture. One embodiment of a method comprises: receiving from a process executing on a first system on chip (SoC) a request for a virtual memory page, the first SoC electrically coupled to a second SoC via an interchip interface, the first SoC electrically coupled to a first local volatile memory device via a first high-performance bus and the second SoC electrically coupled to a second local volatile memory device via a second high-performance bus; determining a free physical page pair comprising a same physical address available on the first and second local volatile memory devices; and mapping the free physical page pair to a single virtual page address.

Abstract: Some implementations provide a multi-layer heat dissipating device that includes a first heat spreader layer, a first support structure, and a second heat spreader layer. The first heat spreader layer includes a first spreader surface and a second spreader surface. The first support structure includes a first support surface and a second support surface. The first support surface of the first support structure is coupled to the second spreader surface of the first heat spreader. The second heat spreader layer includes a third spreader surface and a fourth spreader surface. The third spreader surface of the second heat spreader layer is coupled to the second support surface of the first support structure. In some implementations, the first support structure is a thermally conductive adhesive layer. In some implementations, the first heat spreader layer has a first thermal conductivity, and the first support structure has a second thermal conductivity.

Abstract: Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is compared to an upper bound and a lower bound. If the filtered time information is outside the upper and lower bounds, then an amount of timing compensation for the clock is computed. A signal is sent to reset the clock based on the amount of timing compensation.

Abstract: In a repair of a random access memory (RAM), an error information is received, a fail address of the RAM identified, and a one-time programming applied to a portion of the redundancy circuit while a content of the RAM is valid. Optionally, the RAM is a dynamic access RAM (DRAM), a refresh burst is applied to the DRAM, followed by a non-refresh interval, and the one-time programming is performed during the non-refresh interval.

Abstract: A method includes detecting, at a controller, a rate-of-change between first data traffic to be sent to a dynamic random access memory (DRAM) at a first time and second data traffic to be sent to the DRAM at a second time. The method also includes adjusting a data rate of the second data traffic in response to a determination that the rate-of-change satisfies a threshold.

Abstract: A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page.

Abstract: Systems and methods are disclosed for expanding memory for a system on chip (SoC). A memory card is loaded in an expandable memory socket electrically and is coupled to a system on chip (SoC) via an expansion bus. The memory card comprises a first volatile memory device. In response to detecting the memory card, an expanded virtual memory map is configured. The expanded virtual memory map comprises a first virtual memory space associated the first volatile memory device and a second virtual memory space associated with a second volatile memory device electrically coupled to the SoC via a memory bus. One or more peripheral images associated with the second virtual memory space are relocated to a first portion of the first virtual memory space. A second portion of the first virtual memory space is configured as a block device for performing swap operations associated with the second virtual memory space.

Abstract: A method of controlling signal termination includes providing first logic for selectively terminating signals received at a first device on a bidirectional data bus, providing second logic for selectively terminating signals received at a second device on the bidirectional data bus, sending first signals from the first device to the second device on the bidirectional data bus at a first speed, stopping the sending of the first signals, after stopping the sending of the first signals, enabling the second logic and shifting a reference voltage of the second device from a first level to a second level, after enabling the second logic at the second device, sending second signals from the first device to the second device on the bidirectional data bus at a higher speed, and controlling the first logic based on a speed of signals received at the first device on the bidirectional data bus.

Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device comprises an input/output (I/O) interface, and an I/O voltage controller. The I/O voltage controller is configured to determine a frequency or temperature of the I/O interface, and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

Abstract: Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data.

Abstract: Systems, methods, and computer programs are disclosed for recovering from dynamic random access memory (DRAM) defects. One method comprises determining that an uncorrected bit error has occurred for a physical codeword address associated with a dynamic random access memory (DRAM) device coupled to a system on chip (SoC). A kernel page associated with a DRAM page comprising the physical codeword address is identified as a bad page. Recovery from the uncorrected bit error is provided by rebooting a system comprising the SoC and the DRAM device. In response to the rebooting, the identified kernel page is excluded from being allocated for DRAM operation.

Abstract: Some implementations provide a multi-layer heat dissipating device that includes a first heat spreader layer, a first support structure, and a second heat spreader layer. The first heat spreader layer includes a first spreader surface and a second spreader surface. The first support structure includes a first support surface and a second support surface. The first support surface of the first support structure is coupled to the second spreader surface of the first heat spreader. The second heat spreader layer includes a third spreader surface and a fourth spreader surface. The third spreader surface of the second heat spreader layer is coupled to the second support surface of the first support structure. In some implementations, the first support structure is a thermally conductive adhesive layer. In some implementations, the first heat spreader layer has a first thermal conductivity, and the first support structure has a second thermal conductivity.

Abstract: Methods and systems for an in-system repair process that repairs or attempts to repair random bit failures in a memory device are provided. In some examples, an in-system repair process may select alternative steps depending on whether the failure is correctable or uncorrectable. In these examples, the process uses communications between a system on chip and the memory to fix the failures during normal operation.