Abstract: This invention provides a three-dimensional junctionless neuron network device and a manufacturing method thereof. The device comprises: a substrate; and a stack structure is formed on the surface of the substrate, the stack structure comprises alternately stacked gate electrode layers and isolation layers and has a channel hole penetrating the substrate; a weighting gate layer is formed on the surface of the channel hole, and the weighting gate layer has a gap from the bottom of the channel hole; a gate dielectric layer is located on the weight gate between the layer and the gate electrode layer; a tunneling dielectric layer on the surface of the weighting gate layer; a channel layer filled in the channel hole, the channel layer being in contact with the substrate. The invention adopts a vertically stacked isolation layer and gate layer design. The stack structure has an array of channel holes.

Abstract: An integrated circuit apparatus includes a silicon-on-insulator (SOI) substrate comprising a silicon layer overlying an insulator layer; a first silicon fin region formed in a first region of the silicon layer, the first silicon fin region comprising a first source region, a first drain region, and a first channel region; a second silicon fin region formed in a second region of the silicon layer, the second silicon fin region comprising a second source region, a second drain region, and a second channel region; a gate dielectric layer formed on the first, second, and third surface regions of the first silicon fin region, and on the third and fourth surface regions of the second silicon fin region; a dual-gate FinFET, comprising the second drain, source and channel regions in the second silicon fin region; and a tri-gate FinFET, comprising the first drain, source and channel regions.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel, suspended on the subtract; an N-type semiconductor channel, suspended on the subtract; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; a N-type source region and a N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel.

Abstract: A method for making a tri-gate FinFET and a dual-gate FinFET includes providing a semiconductor on insulator (SOI) wafer having a semiconductor layer over an insulator layer. The method further includes forming a hard mask on the semiconductor layer and patterning the hard mask to form first and second cap portions. The method also includes etching the semiconductor layer to form first and second fins using the first and second cap portions as an etch mask. The method also includes removing the second cap portion to expose the top surface of the second fin and forming a gate dielectric layer on the first and second fins. The method further includes forming a conductive layer over the gate dielectric layer, selectively etching the conductive layer to form first and second gate structures, forming an interlayer dielectric layer over the gate structures, and planarizing the interlayer dielectric layer using the first cap portion as a polish stop.

Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el

Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layers and the channel material layers are doped with different doping types so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.

Abstract: This invention provides a three-dimensional (3D) junction semiconductor memory device and fabrication method thereof. The 3D junction semiconductor memory device comprises a plurality of vertical channel structures and a plurality of gate layers staked up in a vertical direction. The pluralities of vertical channel structures comprise multiple alternatively stacked source/drain material layers and channel material layers in a vertical direction, and the source/drain material layer comprises p type polysilicon, and the channel material layer comprises n type polysilicon so as to constitute a plurality of junction transistors connected in series vertically, such that not only a smaller component size can be achieved, but also more flexible storage unit operation can be achieved.

Abstract: The present invention provides an inversion mode gate-all-around nano-sheet complementary inverter comprises a P-type field effect transistor (FET) and an N-type FET. The P-type FET comprises an N-type semiconductor nano-sheet channel, a first gate dielectric layer fully surround the N-type semiconductor nano-sheet channel, a first gate layer, and a source and a gate area positioned at two ends of the channel. The N-type FET comprises a P-type semiconductor nano-sheet channel, a second gate dielectric layer fully surround the P-type semiconductor nano-sheet channel, a second gate layer, and a source and a gate area positioned at two ends of the channel. The P-type and N-type semiconductor nano-sheet channels are arranged laterally, side by side. The width of the N-type semiconductor nano-sheet channel is greater than that of the P-type semiconductor nano-sheet channel. A common gate electrode is positioned to fully surround the first and second gate layers.

Abstract: A junction-less transistor structure and fabrication method thereof are provided. The method includes providing a semiconductor substrate; and forming an epitaxial layer having a first surface and a second surface on the semiconductor substrate. The method also includes forming a plurality of trenches in the epitaxial layer from the first surface thereof; and forming a gate dielectric layer on side and bottom surfaces of the plurality of trenches. Further, the method includes forming a gate electrode layer on the gate dielectric layer and in the plurality of trenches; and forming an insulation layer on the gate electrode layer. Further, the method also includes forming a drain electrode layer on the first surface of the epitaxial layer; removing the semiconductor substrate; and forming a source electrode layer on the second surface of the epitaxial layer.

Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel suspended on the subtract, a silicon-deuterium passivation layer on the P-type semiconductor channel; an N-type semiconductor channel suspended on the subtract, a silicon-deuterium passivation layer on the N-type semiconductor channel; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel.

Abstract: A fin tunneling field effect transistor (TFET) is disclosed. The fin TFET includes a semiconductor body extending in a first direction on a substrate, wherein the semiconductor body constitutes a channel of the fin TFET. The fin TFET also includes a source and a drain disposed at opposite ends of the semiconductor body, wherein the source is doped with a first dopant type and the drain is doped with a second dopant type, and the first dopant type is different from the second dopant type. The fin TFET further includes a gate disposed on at least two sides of the channel, wherein a portion of the source is disposed in contact with a portion of the channel.

Abstract: The present invention provides a gate-all-around quantum gradient-doped nano-sheet complementary inverter may comprise a P-type field effect transistor (FET) and an N-type FET. The P-type FET may comprise a P-type semiconductor nano-sheet channel, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channel, a first gate layer, and a source and a gate area, arranged at two ends of the channel. The N-type FET may comprise an N-type semiconductor nano-sheet channel, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channel, a second gate layer, and a source and a gate area, arranged at two ends of the channel. A common gate electrode may be arranged to fully surround the first and second gate layers. The doping concentration of the P-type and N-type semiconductor nano-sheet channels, which are arranged laterally, side by side, may be in gradient descent from the surface to the center.

Abstract: The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate el

Abstract: The present invention provides a gate-all-around quantum well complementary inverter comprises a first and a second field effect transistor (FET). Channels of the first and second FETs, each of which is surrounded by a gap area, are juxtaposed transversely. A source area and a drain area are positioned at a side of the channel. The channel comprises a semiconductor nano-sheet, a first semiconductor layer fully surrounding semiconductor nano-sheet and a second semiconductor layer fully surrounding the first semiconductor layer. The first semiconductor layer provides a quantum well for holes, and the second semiconductor layer provides a quantum well for electrons. A common gate electrode fully surrounds the gate layer of the first FET and the gate layer of the second FET. The structure of the disclosed device is compact enough to increase the density and improve the performance and simple enough to produce.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a semiconductor channel, hanging on the subtract; a first semiconductor layer, wrapped all around the semiconductor channel; a second semiconductor layer, wrapped all around the first semiconductor layer; a gate dielectric layer, wrapped all around the second semiconductor layer; and a gate electrode layer, wrapped all around the gate dielectric layer, wherein the first semiconductor layer includes a smaller bandgap than a bandgap of the semiconductor channel. The present inventor includes a quantum well of two dimensional hole gas and a quantum well of two dimensional electron gas, that can improve the electron mobility transistor of holes and electrons, improve the current carrying capacity of N-type Field-Effect Transistor and P-type Field-Effect Transistor, and reduce the resistance and the power consumption.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof.

Abstract: A complementary metal-oxide-semiconductor field-effect transistor comprises a semiconductor substrate, N-type and P-type field-effect transistors positioned in the semiconductor substrate. Each of the field-effect transistors includes a germanium nanowire, a III-V compound layer surrounding the germanium nanowire, a potential barrier layer mounted on the III-V compound layer, a gate dielectric layer, a gate, a source region and a drain region mounted on two sides of the gate. The field-effect transistor can produce two-dimensional electron gases and two-dimensional electron hole gases, and enhance the carrier mobility of the complementary metal-oxide-semiconductor field-effect transistor.

Abstract: A semiconductor device includes a substrate, a cavity in the substrate, and a germanium (Ge) nanowire suspending in the cavity.

Abstract: A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor positioned on the substrate. The n-channel field-effect transistor may include an n-type silicide source portion, an n-type silicide drain portion, and a first n-type channel region. The first n-type channel region may be positioned between the n-type silicide source portion and the n-type silicide drain portion and may directly contact each of the n-type silicide source portion and the n-type silicide drain portion.