Abstract: A semiconductor structure includes: a plurality of transistors located in a semiconductor layer; each of the transistors including a semiconductor body extending in a first direction and a gate structure covering at least one side surface of the semiconductor body; the first direction being a thickness direction of the semiconductor layer; a plurality of conductive pillars, each of the conductive pillars being located on a top surface of a corresponding semiconductor body and being in direct contact with the corresponding semiconductor body; a memory structure covering the plurality of conductive pillars.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate; patterning the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gaps; partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure, relating to the field of semiconductor technology. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, a bit line and a word line; and the substrate includes a semiconductor layer and a spacer. The capacitor structure is arranged on the substrate, and the spacer is positioned between the capacitor structure and at least a part of the semiconductor layer. The transistor structure and the word line are arranged on a side of the capacitor structure distant from the substrate, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word line, and other one of the source and the drain of the transistor structure is electrically connected to the bit line.

Abstract: Embodiment relates to the field of semiconductor technology, and more particularly, to a memory, a semiconductor structure and a formation method thereof. The formation method of the present disclosure includes: providing a substrate; forming a plurality of groups of support pillars spaced apart along a first direction in the substrate, each of the plurality of groups of support pillars being spaced apart along a second direction, the first direction intersecting with the second direction; forming a support layer filling up top gaps between adjacent two of the support pillars; forming an epitaxial pillar on a top of each of the support pillars respectively by means of an epitaxial growth process; and forming a capacitor structure on a surface of a structure jointly constituted by each of the epitaxial pillars and each of the support pillars.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: forming a plurality of first trenches arranged at intervals and extending along a first direction in a base; forming a first insulating layer on a sidewall of the first trench, where a thickness of the first insulating layer is smaller than a target value, and the first insulating layer defines a second trench; performing a silicification reaction on a substrate exposed in the second trench; forming a second insulating layer on a sidewall of the second trench, where the second insulating layer defines a third trench, and a sum of thicknesses of the first insulating layer and the second insulating layer is equal to the target value; and forming an isolation layer in the third trench.

Abstract: A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.

Abstract: A method for forming a memory includes the following operations: a substrate and a semiconductor layer located on the substrate are formed; the semiconductor layer is patterned to form a plurality of first isolation structures and channel regions, each first isolation structure includes a first through hole and a second through hole, and a first isolation pillar located between the first through hole and the second through hole; a first filling layer filling up the first through hole and the second through hole is formed; the first isolation pillar is removed to form a third through hole located in the first filling layer; a barrier layer filling up the third through hole is formed; the channel regions are exposed by removing the first filling layer; and a gate layer covering surfaces of the channel regions is formed.

Abstract: Provided are a semiconductor structure and a method for manufacturing the same, a memory device and a method for manufacturing the same. The semiconductor structure includes at least one transistor. Each of the at least one transistor includes a channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer. The second semiconductor layer introduces strain into the channel.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. The forming method of a semiconductor device includes: providing a substrate; etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses; forming a bit line in the second recesses; forming, at bottoms of the first recesses, an isolation layer covering the bit line; enlarging an inner diameter of the first recess above the isolation layer; and forming a gate layer on a sidewall of the first recess whose inner diameter is enlarged.

Abstract: Embodiments relate to a semiconductor structure, and an array structure and a method for fabricating same. The semiconductor structure includes: a substrate having a bit line structure therein; an active area, where an end of the active area is positioned on the bit line structure, and along a direction perpendicular to the substrate, the active area includes a first channel layer and a second channel layer wrapping at least a bottom surface and part of a sidewall of the first channel layer, and a bottom of the second channel layer is electrically connected to the bit line structure; a word line structure, where the word line structure is positioned on two opposite sides of the active area in the direction perpendicular to the substrate; and a source and a drain respectively positioned at two ends along an extension direction of the active area.

Abstract: A semiconductor structure includes at least one transistor. The transistor includes a channel, a gate, a source, and a drain. The channel includes a first material layer and a second material layer arranged around the first material layer. Resistivity of the first material layer is greater than a first preset value, and resistivity of the second material layer is less than a second preset value, the first preset value being greater than the second preset value. The gate covers at least one side of the channel. The source and the drain are at two ends of an extension direction of the channel.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing the semiconductor structure provided by the present disclosure includes: providing a substrate; forming a base pattern on the substrate, where the base pattern includes a plurality of bit lines arranged in parallel, and an isolation structure is disposed between adjacent two of the bit lines; forming a plurality of semiconductor pillars arranged in a direction of the bit line on a surface of each of the bit lines, where the bit line is electrically connected to the semiconductor pillar; forming a gate-all-around structure on a surface of the semiconductor pillar, where the gate-all-around structure includes a first insulating layer, a gate structure layer, and a second insulating layer that are sequentially disposed on a side surface of the semiconductor pillar.

Abstract: The present disclosure relates to a memory and a memory forming method. The memory forming method includes: providing an initial substrate; etching the initial substrate to form a plurality of capacitor holes and a plurality of recesses that are connected to the capacitor holes in a one-to-one corresponding manner and located below the capacitor holes; forming an isolation layer that connects adjacent ones of the recesses and fills up the recesses, and using the initial substrate remaining below the isolation layer as a substrate; and forming a capacitor in the capacitor hole.

Abstract: Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.

Abstract: Embodiments provide a semiconductor structure and a fabrication method. The method includes: providing a substrate provided with first trenches and including an active pillar positioned between adjacent two of the first trenches; forming, in the active pillar, a second trench whose bottom is greater than or equal to a bottom of the first trench in height; forming a first dielectric layer and a protective layer in the first trench, the first dielectric layer being positioned between the protective layer and the active pillar, and an upper surface of the first dielectric layer being lower than an upper surface of the active pillar; forming second dielectric layers on an exposed side wall of the first trench and a side wall of the second trench, a third trench being formed between each of the second dielectric layers and the protective layer, and a fourth trench being formed between the second dielectric layers.

Abstract: A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.

Abstract: A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.

Abstract: Embodiments relate to a method for fabricating a semiconductor structure. The method includes: providing a substrate, where pillars arranged in an array are formed on a surface of the substrate, and bit lines extending along a first direction are formed at bottoms of the pillars; forming, between adjacent two of the pillars, a first groove extending along a second direction; forming an isolation layer on the substrate, where the isolation layer is filled in the first groove and is filled between adjacent two of the bit lines; etching the isolation layer to expose a surface of the pillar, where a first sub isolation layer positioned in the first groove is lower than a second sub isolation layer; forming a word line surrounding a side wall of the pillar, where a surface of the word line is not higher than a surface of the second sub isolation layer; and forming a dielectric layer on the word line.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming an silicon pillar on the substrate; preprocessing the silicon pillar, to form an active pillar including a first segment, a second segment, and a third segment, where the second segment includes a first sub-segment and a second sub-segment, and a cross-sectional area of the second sub-segment is smaller than that of the first sub-segment; forming a gate oxide layer; and forming a word line structure surrounding the second segment, where the word line structure includes a first word line structure and a second word line structure that are made of different materials.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars on the substrate, where each of the active pillars includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.