Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: A semiconductor structure includes a substrate and a plurality of word lines located on a top surface of the substrate. Each of the word lines extends in a direction perpendicular to the top surface of the substrate. The plurality of word lines are arranged at intervals along a first direction. Any two adjacent ones of the word lines are arranged in an at least partially staggered manner along the first direction. The first direction is a direction parallel to the top surface of the substrate.

Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

Abstract: Embodiments of the disclosure provide a semiconductor structure, a method for manufacturing the same and a memory. The semiconductor structure includes a plurality of active pillars and a plurality of conductor lines. Each of the conductor lines includes a plurality of metal layers located in a gap between two adjacent active pillars and a metal compound layer partially surrounding the plurality of active pillars.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The method for manufacturing the semiconductor structure includes: a substrate is provided: a plurality of semiconductor channels arrayed in a first direction and a second direction are formed on the substrate: a plurality of bit lines extending in the first direction are formed, in which the bit lines is located in the substrate: and a plurality of word lines extending in the second direction are formed, in which two word lines adjacent to each other in the first direction are spaced apart from each other in a direction perpendicular to a surface of the substrate: and a sidewall conductive layer is formed, in which the sidewall conductive layer is located above one of the two word lines adjacent to each other, and is arranged in the same layer as the other of the two word lines.

Abstract: The method for forming the capacitor stack structure includes: providing a substrate on which a plurality of first laminated structures arranged in a first direction and a first isolation structure located between every two adjacent the first laminated structures are formed, and the first laminated structure including first semiconductor layers and second semiconductor layers stacked alternately; forming, in the first laminated structures and the first isolation structures, first trench extending in the first direction, the spacing in a second direction between the adjacent remaining first semiconductor layers is greater than the spacing between the adjacent remaining second semiconductor layers; forming a support structure in the first trench, and removing the first semiconductor layers from the first laminated structure to form a first space; and forming capacitor structures in the first space to form a capacitor stack structure.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple semiconductor pillars, memory structures, and multiple transistors. The multiple semiconductor pillars are arrayed along a first direction and a second direction. Each semiconductor pillar includes a first portion and a second portion on the first portion. The memory structure includes a first electrode layer, a dielectric layer and a second electrode layer. The first electrode layers cover sidewalls of the first portions and are located in first filling regions arranged at intervals. Each first filling region surrounds a sidewall of the first portion. The dielectric layers cover at least surfaces of the first electrode layers. The second electrode layers cover surfaces of the dielectric layers. Channel structures of the transistors are located in the second portions, and extend in a same direction as the second portions.

Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.

Abstract: A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided, which relate to the technical field of semiconductors. The semiconductor structure includes a substrate and a plurality of first conductive layers. The substrate includes a plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction. A plurality of active pillars are provided between the plurality of first trenches and the plurality of second trenches. The first direction intersects with the second direction. Each of the plurality of first conductive layers is arranged on each of sidewalls, which are arrayed in the first direction, of a respective one of the plurality of active pillars.

Abstract: A semiconductor structure includes: a substrate, a first gate structure, and a second gate structure. The substrate includes: discrete first semiconductor pillars arranged at a top of the substrate and extending in a vertical direction; and a second semiconductor pillar and a third semiconductor pillar extending in the vertical direction, the second and third semiconductor pillars are provided at a top of each first semiconductor pillar. The first gate structure is arranged in a middle region of the first semiconductor pillar and surrounds the first semiconductor pillar. The second gate structure is arranged in a middle region of the second semiconductor pillar and of the third semiconductor pillar, and includes a first ring structure and a second ring structure. The first ring structure surrounds the second semiconductor pillar, and the second ring structure surrounds the third semiconductor pillar.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a substrate, a gate structure and a dielectric layer. Herein, the substrate includes discrete semiconductor pillars. The semiconductor pillars are arranged at the top of the substrate and extend in a vertical direction. The substrate further includes a capacitor structure located at the top of the semiconductor pillar. The gate structure is arranged at the middle area of the semiconductor pillar and surrounds the semiconductor pillar. The dielectric layer is located between the gate structure and the semiconductor pillar, and covers the sidewall of the semiconductor pillar.

Abstract: A semiconductor structure and a method for preparing a semiconductor structure are provided. The semiconductor structure includes a substrate. A first active area, a second active area and an isolation structure are arranged on the substrate. The first active area and the second active area are isolated from one another by the isolation structure. The first active area includes a first doped region and a second doped region. The second active area includes a third doped region and a fourth doped region. The semiconductor structure further includes a gate structure. The gate structure is arranged above the second doped region and the third doped region, and the gate structure is connected to the second doped region and the third doped region.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The semiconductor structure includes: a substrate, first gate structures, second gate structures, and a covering layer. The substrate includes semiconductor channels spaced apart from each other and arranged at a top portion of the substrate and extending in a vertical direction. Each first gate structure is arranged in a first area of a respective semiconductor channel and is arranged around the respective semiconductor channel. Each second gate structure is arranged in a second area of a respective semiconductor channel and includes a ring structure and at least one bridge structure. The covering layer is arranged in a spaced area between any two adjacent semiconductor channels. The covering layer includes first interconnecting holes extending in the vertical direction.

Abstract: A semiconductor structure includes a substrate, and a plurality of first semiconductor columns, a storage structure, a plurality of transistors and a first protective layer located above the substrate. The plurality of first semiconductor columns are arranged in array in first and second directions. Each first semiconductor column includes a first part and a second part located on same. The second part includes a bottom portion, an intermediate portion and a top portion. The first direction and the second direction intersect with each other and are both parallel to top surface of the substrate. The storage structure surrounds sidewalls of the first parts. The first protective layer surrounds sidewalls of the top portions of the second parts. A channel structure of each transistor is located in the intermediate portion of the second part, and an extending direction of the channel structure is the same as that of the second part.

Abstract: A semiconductor structure, a method for manufacturing the same and a memory are provided. The semiconductor structure includes a substrate, multiple first active pillars above the substrate, a memory structure, multiple transistors, and multiple second active pillars. The multiple first active pillars are arranged in an array along a first direction and a second direction. The substrate includes an isolation structure on which the first active pillars are located. The memory structure includes first electrode layers, a dielectric layer and a second electrode layer. The first electrode layer covers a sidewall of the first active pillar, the dielectric layer covers at least surfaces of the first electrode layers, the second electrode layer covers a surface of the dielectric layer. Each of the second active pillars is located above a corresponding one of the first active pillars; a channel structure of each transistor is located in the second active pillar.

Abstract: A semiconductor structure and a method for manufacturing the same, and a memory are provided. The semiconductor structure includes: a substrate, a plurality of oxide pillars, a plurality of active pillars, a first insulating layer and a storage structure. The plurality of oxide pillars are on the substrate and arranged in an array along a first direction and a second direction. Both the first direction and the second direction are parallel to a surface of the substrate, and the first direction intersects with the second direction. The first insulating layer is in a gap between the oxide pillars. Each active pillar is on a top surface of a corresponding one of the oxide pillars. The storage structure covers at least part of a side wall of the active pillar.

Abstract: A semiconductor structure includes a base, a dielectric layer, a gate structure, and a covering layer. The base includes discrete semiconductor pillars. The semiconductor pillars are disposed at the top of the base and extend in a vertical direction. The dielectric layer covers the sidewall of the semiconductor pillar. The gate structure is disposed in the middle area of the semiconductor pillar. The gate structure includes a gate-all-around structure, the gate-all-around surrounding the semiconductor pillar. A first part of the dielectric layer is disposed between the gate structures and the semiconductor pillars. The covering layer covers the top of the semiconductor pillar and part of the sidewall close to the top. The material of the covering layer includes a boron-containing compound.

Abstract: A semiconductor structure includes a substrate, a gate structure, a cover layer and a first sacrificial structure. The substrate includes discrete semiconductor channels arranged at a top of the substrate. The gate structure is disposed in a middle region of a semiconductor channel, and includes a ring structure and a bridge structure. The ring structure encircles the semiconductor channel, and the bridge structure penetrates through the semiconductor channel and extends to an inner wall of the ring structure along a penetrating direction. The cover layer is located between adjacent semiconductor channels, and includes a first communication hole. The first sacrificial structure is located on the cover layer, and includes a second communication hole. An inner sidewall of the second communication hole has an irregular shape.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes: a substrate, a dielectric layer, a first gate structure and a second gate structure. The substrate includes discrete semiconductors arranged at a top of the substrate and extending in a vertical direction. The first gate structure is arranged in a first region of the semiconductor pillar and surrounds the semiconductor pillar. The second gate structure is arranged in a second region of the semiconductor pillar and includes a ring structure and at least one bridge structure. The ring structure surrounds the semiconductor pillar, and the at least one bridge structure penetrates through the semiconductor pillar and extends to an inner wall of the ring structure in a penetrating direction. The dielectric layer is located between the first gate structure and the semiconductor pillar, and between the second gate structure and the semiconductor pillar.