Patents by Inventor Dharmendra S. Modha

Dharmendra S. Modha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10929747
    Abstract: One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10891544
    Abstract: The present invention provides an event-driven universal neural network circuit. The circuit comprises a plurality of neural modules. Each neural module comprises multiple digital neurons such that each neuron in a neural module has a corresponding neuron in another neural module. An interconnection network comprising a plurality of digital synapses interconnects the neural modules. Each synapse interconnects a first neural module to a second neural module by interconnecting a neuron in the first neural module to a corresponding neuron in the second neural module. Corresponding neurons in the first neural module and the second neural module communicate via the synapses. Each synapse comprises a learning rule associating a neuron in the first neural module with a corresponding neuron in the second neural module. A control module generates signals which define a set of time steps for event-driven operation of the neurons and event communication via the interconnection network.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventor: Dharmendra S. Modha
  • Patent number: 10885424
    Abstract: A neural system comprises multiple neurons interconnected via synapse devices. Each neuron integrates input signals arriving on its dendrite, generates a spike in response to the integrated input signals exceeding a threshold, and sends the spike to the interconnected neurons via its axon. The system further includes multiple noruens, each noruen is interconnected via the interconnect network with those neurons that the noruen's corresponding neuron sends its axon to. Each noruen integrates input spikes from connected spiking neurons and generates a spike in response to the integrated input spikes exceeding a threshold. There can be one noruen for every corresponding neuron. For a first neuron connected via its axon via a synapse to dendrite of a second neuron, a noruen corresponding to the second neuron is connected via its axon through the same synapse to dendrite of the noruen corresponding to the first neuron.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventor: Dharmendra S. Modha
  • Publication number: 20200379841
    Abstract: A computer-implemented method according to one embodiment includes, prior to an execution of a deterministic program, determining a pre-computed check sequence for a first plurality of values associated with the execution of the deterministic program, during the execution of the deterministic program, determining a runtime check sequence for a second plurality of values associated with the execution of the deterministic program, comparing the pre-computed check sequence to the runtime check sequence; and identifying one or more errors associated with the execution of the deterministic program, based on the comparing.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Andrew S. Cassidy, Dharmendra S. Modha, John V. Arthur, Jun Sawada
  • Patent number: 10846567
    Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 24, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Andreopoulos, Rathinakumar Appuswamy, Pallab Datta, Steven K. Esser, Dharmendra S. Modha
  • Publication number: 20200364535
    Abstract: Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.
    Type: Application
    Filed: October 29, 2018
    Publication date: November 19, 2020
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 10838860
    Abstract: Memory-mapped interfaces for message passing computing systems are provided. According to various embodiments, a write request is received. The write request comprises write data and a write address. The write address is a memory address within a memory map. The write address is translated into a neural network address. The neural network address identifies at least one input location of a destination neural network. The write data is sent via a network according to the neural network address to the at least one input location of the destination neural network. A message is received via the network from a source neural network. The message comprises data and at least one address. A location in a buffer is determined based on the at least one address. The data is stored at the location in the buffer. The buffer is accessible via the memory map.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Filipp A. Akopyan, John V. Arthur, Andrew S. Cassidy, Michael V. DeBole, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10839287
    Abstract: Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 10832151
    Abstract: Embodiments of the invention relate to implementing a probabilistic graphical model (PGM) using magnetic tunnel junctions (MTJs). One embodiment comprises a memory array of magnetic tunnel junctions and a driver unit for programming the memory array to represent a probabilistic graphical model. The magnetic tunnel junctions are organized into multiple subsets of magnetic tunnel junctions. The driver unit selectively applies an electrical pulse to a subset of magnetic tunnel junctions to program information representing a probabilistic belief state in said subset of magnetic tunnel junctions.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bryan L. Jackson, Dharmendra S. Modha
  • Patent number: 10832121
    Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rathinakumar Appuswamy, Myron D. Flickner, Dharmendra S. Modha
  • Patent number: 10831595
    Abstract: A computer-implemented method according to one embodiment includes, prior to an execution of a deterministic program, determining a pre-computed check sequence for a first plurality of values associated with the execution of the deterministic program, during the execution of the deterministic program, determining a runtime check sequence for a second plurality of values associated with the execution of the deterministic program, comparing the pre-computed check sequence to the runtime check sequence; and identifying one or more errors associated with the execution of the deterministic program, based on the comparing.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Andrew S. Cassidy, Dharmendra S. Modha, John V. Arthur, Jun Sawada
  • Patent number: 10832125
    Abstract: One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a metadata analysis unit for analyzing metadata information associated with one or more portions of an adjacency matrix representation of the neural network, and a mapping unit for mapping the one or more portions of the matrix representation onto the neurosynaptic substrate based on the metadata information.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Arnon Amir, Rathinakumar Appuswamy, Pallab Datta, Myron D. Flickner, Paul A. Merolla, Dharmendra S. Modha, Benjamin G. Shaw
  • Patent number: 10810487
    Abstract: A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 20, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bernard V. Brezzo, Leland Chang, Steven K. Esser, Daniel J. Friedman, Yong Liu, Dharmendra S. Modha, Robert K. Montoye, Bipin Rajendran, Jae-sun Seo, Jose A. Tierno
  • Patent number: 10782726
    Abstract: In one embodiment, a computer program product for optimizing core utilization in a neurosynaptic network includes a computer readable storage medium having program instructions embodied therewith, where the computer readable storage medium is not a transitory signal per se, and where the program instructions are executable by a processor to cause the processor to perform a method including identifying, by the processor, one or more unused portions of a neurosynaptic network, and for each of the one or more unused portions of the neurosynaptic network, disconnecting, by the processor, the unused portion from the neurosynaptic network.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Arnon Amir, Pallab Datta, Nimrod Megiddo, Dharmendra S. Modha
  • Patent number: 10785745
    Abstract: Embodiments of the invention provide a system for scaling multi-core neurosynaptic networks. The system comprises multiple network circuits. Each network circuit comprises a plurality of neurosynaptic core circuits. Each core circuit comprises multiple electronic neurons interconnected with multiple electronic axons via a plurality of electronic synapse devices. An interconnect fabric couples the network circuits. Each network circuit has at least one network interface. Each network interface for each network circuit enables data exchange between the network circuit and another network circuit by tagging each data packet from the network circuit with corresponding routing information.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10769519
    Abstract: One embodiment of the invention provides a system comprising at least one data-to-spike converter unit for converting input numeric data received by the system to spike event data. Each data-to-spike converter unit is configured to support one or more spike codes.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: September 8, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada, Benjamin G. Shaw
  • Patent number: 10755165
    Abstract: One embodiment of the invention provides a system comprising at least one spike-to-data converter unit for converting spike event data generated by neurons to output numeric data. Each spike-to-data converter unit is configured to support one or more spike codes.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, Andrew S. Cassidy, Steven K. Esser, Myron D. Flickner, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada, Benjamin G. Shaw
  • Patent number: 10755166
    Abstract: Embodiments of the present invention provide a method for feature extraction using multiple neurosynaptic core circuits including one or more input core circuits for receiving input and one or more output core circuits for generating output. The method comprises receiving a set of input data via the input core circuits, and extracting a first set of features from the input data using the input core circuits. Each feature of the first set of features is based on a subset of the input data. The method further comprises reordering the first set of features using the input core circuits, and generating a second set of features by combining the reordered first set of features using the output core circuits. The second set of features comprises a set of features with reduced correlation. Each feature of the second set of features is based on the entirety of said set of input data.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rathinakumar Appuswamy, Myron D. Flickner, Dharmendra S. Modha
  • Patent number: 10740282
    Abstract: Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Rodrigo Alvarez-Icaza Rivera, John V. Arthur, John E. Barth, Jr., Andrew S. Cassidy, Subramanian S. Iyer, Bryan L. Jackson, Paul A. Merolla, Dharmendra S. Modha, Jun Sawada
  • Patent number: 10725494
    Abstract: Reduction in the number of neurons and axons in a neurosynaptic network while maintaining its functionality is provided. A neural network description describing a neural network is read. One or more functional unit of the neural network is identified. The one or more functional unit of the neural network is optimized. An optimized neural network description is written based on the optimized functional unit.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arnon Amir, Pallab Datta, Dharmendra S. Modha