Abstract: In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract: A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.

Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch.

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.

Abstract: Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap.

Abstract: A semiconductor structure includes a first metal-containing layer, a dielectric capping layer, a second metal-containing layer, and a conductive pad. The first metal-containing layer includes a set of metal structures, a dielectric filler disposed to occupy a portion of the first metal-containing layer, and an air-gap region defined by at least the set of metal structures and the dielectric filler and abutting at least a portion of the set of metal structures. The second metal-containing layer includes at least a via plug electrically connected to a portion of the set of metal structures. The conductive pad and the via plug do not overlap the air-gap region.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.

Abstract: In order to protect IMD layers, particularly low-k dielectrics, a protection film is formed on the sidewall of an opening in the IMD layers prior to etching a trench in the underlying silicon substrate. After etching the trench, such as through a TMAH wet etch, at least part of the protection film can be removed. The protection film can be removed in an anisotropic etch process such that a portion of the protection film remains as a sidewall spacer on the sidewall of the opening within the IMD layers.

Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.

Abstract: A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.

Abstract: Within an option selection device structure and a method for fabrication thereof there is formed a terminal metal layer and an option selection device at a co-planar level over a microelectronic substrate. The option selection device is passivated with: (1) a terminal metal passivation layer having an etch stop layer within its thickness; and (2) a bond pad passivation layer. There is simultaneously also formed through the bond pad passivation layer: (1) a via which accesses a bond pad formed contacting the terminal metal layer; and (2) an aperture over the option selection device which stops at the etch stop layer.

Abstract: Within a method for fabricating a microelectronic fabrication there is employed a patterned positive photoresist residue layer as a protective layer within an aperture when processing an upper region of a topographic microelectronic layer having formed therein the aperture. The patterned positive photoresist residue layer is formed employing an incomplete vertical, but complete horizontal, blanket photoexposure and development of a blanket positive photoresist layer formed upon the topographic microelectronic layer and filling the aperture. The method provides the microelectronic fabrication with enhanced reliability.

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.

Abstract: An improved method of forming a dual damascene structure by a via first process is described. Via holes are formed in a damascene stack consisting of an etch stop layer, a dielectric layer, and a barrier layer. An i-line photoresist is coated on the substrate and fills the vias. An e-beam curing step is performed to render the photoresist components inactive towards adjacent layers. The photoresist is etched back to a level about 1600 Angstroms above the via bottom to form a plug. A second curing step may be performed and then a Deep UV resist is preferably coated and patterned to form a trench opening above the vias. There is no interaction between the Deep UV photoresist and the cured plug which thereby prevents scum or bridging defects from occurring. Fences during trench etch are avoided. Plug stabilization also prevents voids from forming during trench patterning.

Abstract: Within an option selection device structure and a method for fabrication thereof there is formed a terminal metal layer and an option selection device at a co-planar level over a microelectronic substrate. The option selection device is passivated with: (1) a terminal metal passivation layer having an etch stop layer within its thickness; and (2) a bond pad passivation layer. There is simultaneously also formed through the bond pad passivation layer: (1) a via which accesses a bond pad formed contacting the terminal metal layer; and (2) an aperture over the option selection device which stops at the etch stop layer.