Abstract: A metal-insulator-metal (MIM) capacitor structure includes a semiconductor substrate and a bottom conductive layer above the semiconductor substrate. The bottom conductive layer has a slanted sidewall with respect to a top surface of the semiconductor substrate. The MIM capacitor structure further includes a top conductive layer above the bottom conductive layer. The top conductive layer has a vertical sidewall with respect to the top surface of the semiconductor substrate. The MIM capacitor structure further includes an insulating layer interposed between the bottom conductive layer and the top conductive layer. The insulating layer covers the slanted sidewall of the bottom conductive layer.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a method for integrated circuit (IC) fabrication includes forming a passivation layer over a first contact feature, forming a second contact feature over and through the passivation layer to electrically connect to the first contact feature, and forming a multi-layer passivation structure over the second contact feature and over the passivation layer. Forming the multi-layer passivation structure includes depositing a first nitride layer, an oxide layer over the first nitride layer, and a second nitride layer over the oxide layer.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: A semiconductor structure comprises a first conductive material-containing layer. The first conductive material-containing layer comprises a dielectric material, at least two conductive structures in the dielectric material, and an air-gap region in the dielectric material between the at least two conductive structures. The semiconductor structure also comprises a capping layer over the at least two conductive structures and the air-gap region. The semiconductor structure further comprises a second conductive material-containing layer over the capping layer. The second conductive material-containing layer comprises a via plug electrically connected to one of the at least two conductive structures. The via plug is separated from the air-gap region by at least a first predetermined distance. The semiconductor structure additionally comprises a conductive pad over the second conductive material-containing layer. The conductive pad is offset from the air-gap region by at least a second predetermined distance.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for forming the same are provided. The MIM capacitor structure includes a substrate, a bottom electrode layer, a first dielectric layer, a top electrode layer and first dielectric spacers. The bottom electrode layer is positioned over the substrate. The first dielectric layer is positioned over the bottom electrode layer. The top electrode layer is positioned over the first dielectric layer. The first dielectric spacers are positioned on opposite sidewalls of the bottom electrode layer. The first dielectric layer has a first dielectric constant. The first dielectric spacers have a second dielectric constant that is lower than the first dielectric constant.

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.