MASK-SHIFT-AWARE RC EXTRACTION FOR DOUBLE PATTERNING DESIGN
A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
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This disclosure relates generally to integrated circuit design, and more particularly to forming integrated circuits using double-patterning technology.
BACKGROUNDDouble patterning is a technology developed for lithography to enhance the feature density. Typically, for forming features of integrated circuits on wafers, lithography technology is used, which involves applying a photo resist, and defining patterns on the photo resist. The patterns in the patterned photo resist are first defined in a lithography mask, and are implemented either by the transparent portions or by the opaque portions in the lithography mask. The patterns in the patterned photo resist are then transferred to the manufactured features.
With the increasing down-scaling of integrated circuits, the optical proximity effect posts an increasingly greater problem. When two separate features are too close to each other, the optical proximity effect may cause the features to short to each other. To solve such a problem, double patterning technology is introduced. The closely located features are separated to two masks of a same double-patterning mask set, with both masks used to expose the same photo resist. In each of the masks, the distances between features are increased over the distances between features in the otherwise a single mask, and hence the optical proximity effect is reduced, or substantially eliminated.
After the foundary receives the layout design, a layout decomposition is performed to separate the metal lines, for example, according to the double patterning design rules. Lithograph processes are performed to implement the layout on wafers. However, it was found that there was a mismatch between the simulated performance value (step 114) and the performance value measured from the actual wafers. One of the reasons is that when the lithography processes are performed, there may be a relative shift between the two lithography masks of a same double patterning mask. Such shift, however, was not reflected in the estimation of the performance values.
SUMMARYIn accordance with one aspect, a method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.
Other embodiments are also disclosed.
For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure.
A novel method of finding optimum decomposition schemes and estimating the performance values of integrated circuits is provided. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.
Techfiles may be established to reflect the capacitance between patterns A and B as functions of spacing S and width W (shown in
Referring to
If a transition shift occurs to cause mask shift Δs_mask (
C′—ab=C—ab+SC12*(−Δs_mask) [Eq. 1]
C′—bc=C—bc+SC23*(+Δs_mask) [Eq. 2]
Wherein SC12 is the sensitivity (
Since mask shift Δs_mask may include the mask shift Δx in the x direction and the mask shift Δy in the y direction, the new capacitance C (with the mask shift) between two patterns may be expressed as:
is the sensitivity of capacitance to the mask shift in x direction, and
is the sensitivity of capacitance to the mask shift in y direction, and C0 is the capacitance if no mask shift occurs. Equation 3 may further be modified to include the factors of magnification shift and the rotation shift.
In an embodiment, the capacitances between patterns (
Further, the techfile item “C1 A B 5.6e-15*SC 1:−0.048 2:−0.024” represents that the capacitance C1 between nodes A and B is 5.6e-15 farads if no mask shift occurs, and the sensitivity of capacitance is −0.048 in layer M1 (for mask shifts in the x direction), and is −0.024 in layer M1 (for mask shifts in the y direction). Accordingly, with such a techfile, if a mask shift is known (or is assumed), the respective capacitance as a result of the mask shift may be calculated using the techfile and Equation 3.
As addressed in preceding paragraphs when the integrated circuit (layout) is manufactured on wafers, masks mask1 and mask2 may have a mask shift with relative to each other, which includes a transition shift, a magnification shift, and/or a rotation shift (
Next, in step 23, mask shifts are defined, and may include Δx and Δy that are transition shifts. In addition, mask shifts may also include the magnification shift and the rotation shift. In the techfiles, the maximum mask shift for each of the metal layers has been defined. Accordingly, mask shifts Δx and Δy are defined as being within the range of the maximum shifts as defined in the techfiles. For example, as shown in
Since the actual mask shift may be at any value less than the maximum mask shift, the range defined by the maximum shift may be divided into steps, and for each of the steps, the performance value of the circuit may be simulated. For example, assuming a maximum shift is 0.02, then it can be assumed that the actual mask shift may be 0.005, 0.01, 0.015, or 0.02. For each of these four assumed mask shifts, the performance values of the circuit may be simulated. Referring to
Similar to the mask shift in the x direction, the mask shift in the y direction also has a maximum shift, as also shown in
In alternative embodiments, the maximum mask shifts listed in the techfiles are used directly to calculate the performance value without being divided into steps. Accordingly, for each of the decompositions, the calculation is much faster.
Next, as shown in step 26, the corresponding performance values, such as the timing (of critical paths, for example) and noise, for each of the above-discussed mask shift combinations may be simulated using the capacitances already calculated in step 24. The methods for simulating the performance values from the capacitances are known in the art, and hence are not discussed herein. The performance values obtained from different mask shift combinations are compared to find the worst-case performance value, for example, the worst timing of critical paths. Again, although the actual mask shift at manufacturing time cannot be predicted, the performance value of the circuit when the worst-case scenario occurs is already obtained, and will be recorded in step 28.
The worst-case performance value obtained in preceding steps is for one of the decompositions, a loop is used to calculate/estimate the worst-case performance value for each of the available decompositions obtained in step 20. In the loop, it is determined (step 30) whether the worst-case performance values of all decompositions have been calculated, and if not, a calculation is performed for the next decomposition. If the worst-case performance values of all decompositions have been calculated, the worst-case performance values are exported (step 32) for further examination. In an embodiment, the decomposition whose worst-case performance value is the best among the worst-case performance values of all decompositions may be selected (step 34), and is used to make physical double patterning lithography masks mask1 and mask2. The integrated circuit will then be manufactured on wafer using the selected decomposition.
With the worst-case performance values being estimated, designer, at the time of design, may perform a design margin analysis and check whether the worst-case performance, such as the worst-case timing or the worse-case noise, is in the design margin or not. Further, with the adoption of the decomposition whose worst-case performance value being the best among all available decompositions, foundaries may manufacture integrated circuits using the best decomposition scheme.
Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.
Claims
1. A method comprising:
- providing a layout of an integrated circuit design;
- generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions comprising patterns separated to a first mask and a second mask of a double patterning mask set;
- determining a maximum shift between the first and the second masks, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer; and
- for each of the plurality of double patterning decompositions, simulating a worst-case performance value, wherein the step of simulating is performed using mask shifts within a range defined by the maximum shift.
2. The method of claim 1 further comprising:
- comparing the worst-case performance values of the plurality of double patterning decompositions;
- selecting a decomposition from the plurality of double patterning decompositions, wherein the worst-case performance value of the decomposition is the best among the worst-case performance values of the plurality of double patterning decompositions; and
- using the decomposition to perform double patterning lithography steps on wafers.
3. The method of claim 1 further comprising:
- generating a techfile comprising: capacitances of patterns in the layout as a function of spacings between the patterns; and capacitance sensitivities of the capacitances to changes in the spacings, wherein the techfile is used in the step of simulating the worst-case performance value of the each of the plurality of double patterning decompositions.
4. The method of claim 4 further comprising:
- retrieving a capacitance from the techfile;
- calculating a new capacitance using the capacitance and one of the mask shifts by adding a product of the one of the mask shifts and a respective one of the capacitance sensitivities to the capacitance; and
- using the new capacitance to calculate a performance value of the integrated circuit design, with the performance value corresponding to the one of the mask shifts.
5. The method of claim 4, wherein the step of calculating the new capacitance is performed using a equation: C = C 0 + ∂ Cx ∂ x ( ± Δ x ) ++ ∂ Cy ∂ y ( ± Δ y ) wherein C is the new capacitance, Co is the capacitance without any mask shift, ∂ C x ∂ x is a sensitivity of the capacitance to a mask shift in x direction, ∂ Cy ∂ y is a sensitivity of the capacitance to a mask shift in y direction, Δx is the mask shift in the x direction, and Δy is the mask shift in the y direction.
6. The method of claim 1, wherein the worst-case performance value comprises a timing of a critical path of the layout.
7. The method of claim 1, wherein the worst-case performance value comprises a noise of a critical path of the layout.
8. A method comprising:
- providing a layout of an integrated circuit design;
- generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions comprising patterns separated to a first mask and a second mask of a double patterning mask set;
- determining capacitances of patterns in the layout as a function of spacings between the patterns;
- determining capacitance sensitivities of the patterns as a function of ranges of the spacings;
- determining a maximum shift between the first and the second masks, wherein the maximum shift is a maximum expected shift in a manufacturing process for implementing the layout on a silicon wafer;
- calculating a new capacitance of the patterns using the maximum shift;
- for each of the plurality of double patterning decompositions, using the new capacitance to calculate a performance value;
- comparing the performance values of the plurality of double patterning decompositions to select one of the plurality of double patterning decompositions, with the performance value of the one of the plurality of double patterning decompositions being the best among all of the plurality of double patterning decompositions; and
- manufacturing a double pattering mask set using the one of the plurality of double patterning decompositions.
9. The method of claim 8, wherein the capacitances are functions of widths of the patterns.
10. The method of claim 8 further comprising storing the capacitances of the patterns in the layout as a function of the spacings between the patterns into a techfile.
11. The method of claim 10 further comprising storing capacitance sensitivities of the patterns as a function of ranges of the spacings into the techfile.
12. The method of claim 8 further comprising:
- generating a plurality of possible mask shifts, with the plurality of possible mask shifts being in a range defined by the maximum shift;
- calculating additional new capacitances of the patterns using the plurality of possible mask shifts;
- using the additional new capacitances to calculate additional performance values;
- comparing the additional performance values and the performance value to determine a worst-case performance value for a respective decomposition, wherein the worst-case performance value is the worst among the additional performance values and the performance value; and
- performing the step of selecting the one of the plurality of double patterning decompositions, wherein the worst-case performance value of the one of the plurality of double patterning decompositions is the best among the plurality of double patterning decompositions.
13. The method of claim 8, wherein the performance value comprises a timing of a critical path of the layout.
14. The method of claim 8, wherein the performance value comprises a noise of a critical path of the layout.
15. A method comprising:
- providing a layout of an integrated circuit design;
- generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions comprising patterns separated to a first mask and a second mask of a double patterning mask set;
- determining a maximum shift between the first and the second masks, wherein the maximum shift is a maximum expected shift in a manufacturing process for implementing the layout on a wafer;
- for each of the plurality of double patterning decompositions: generating a plurality of possible mask shifts, with the plurality of possible mask shifts being in a range defined by the maximum shift; calculating new capacitances between the patterns using the plurality of possible mask shifts and the maximum mask shift; using the new capacitances to calculate performance values; selecting a worst-case performance value from the performance values; and designating the worst-case performance value as being the worst-case performance value of the each of the plurality of double patterning decompositions;
- selecting one of the plurality of double patterning decompositions, with the worst-case performance value of the one of the plurality of double patterning decompositions being the best among all of the plurality of double patterning decompositions; and
- implementing the layout on the wafer using the one of the plurality of double patterning decompositions.
16. The method of claim 15, wherein the step of calculating the new capacitances is performed using a equation: C = C 0 + ∂ Cx ∂ x ( ± Δ x ) ++ ∂ Cy ∂ y ( ± Δ y ) wherein C is one of the new capacitances, C0 is a capacitance without any mask shift, ∂ C x ∂ x is a sensitivity of the one of the new capacitances to a mask shift in x direction, ∂ Cy ∂ y is a sensitivity of the one of the new capacitances to a mask shift in y direction, Δx is the mask shift in the x direction, and Δy is the mask shift in the y direction.
17. The method of claim 16, wherein the capacitance without any mask shift, the sensitivity of the one of the new capacitances to the mask shift in the x direction, and the one of the new capacitances to the mask shift in the y direction are stored in a techfile.
18. The method of claim 16, wherein the capacitance without any mask shift is a function of widths of the patterns.
19. The method of claim 15, wherein the performance values comprise timings of critical paths of the layout.
20. The method of claim 15, wherein the performance values comprise a noise of the layout.
Type: Application
Filed: Aug 31, 2010
Publication Date: Mar 1, 2012
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Lee-Chung Lu (Taipei), Yi-Kan Cheng (Taipei), Hsiao-Shu Chao (Baoshan Township), Ke-Ying Su (Hsin-Chu), Cheng-Hung Yeh (Jhunan Township), Dian-Hau Chen (Hsin-Chu), Ru-Gun Liu (Hsin-Chu), Wen-Chun Huang (Tainan)
Application Number: 12/872,938
International Classification: G03C 7/20 (20060101);