Patents by Inventor Didier Dutartre
Didier Dutartre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8603887Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.Type: GrantFiled: July 27, 2012Date of Patent: December 10, 2013Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SAS, International Business Machines CorporationInventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
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Patent number: 8524522Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.Type: GrantFiled: December 9, 2010Date of Patent: September 3, 2013Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
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Publication number: 20130072032Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.Type: ApplicationFiled: July 27, 2012Publication date: March 21, 2013Applicants: STMicroelectronics S.A., International Business Machines Corporation, STMicroelectronics (Crolles 2) SASInventors: Didier Dutartre, Nicolas Breil, Yves Campidelli, Olivier Gourhant
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Publication number: 20120252174Abstract: A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.Type: ApplicationFiled: March 30, 2012Publication date: October 4, 2012Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.Inventors: Didier Dutartre, Nicolas Loubet, Yves Campidelli, Denis Pellissier-Tanon
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Patent number: 8168536Abstract: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.Type: GrantFiled: April 11, 2008Date of Patent: May 1, 2012Assignee: STMicroeletronics S.A.Inventors: Didier Dutartre, Philippe Coronel, Nicolas Loubet
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Patent number: 8158495Abstract: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.Type: GrantFiled: April 18, 2007Date of Patent: April 17, 2012Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Laurent Rubaldo, Alexandre Talbot
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Publication number: 20110140220Abstract: A process for producing a microelectronic device includes producing a first semiconductor substrate which includes a first layer and a second layer present between a first side and a second side of the substrate. First electronic components and an interconnecting part are produced on and above the second side. The substrate is then thinned by a first selective etch applied from the first side and stopping on the first layer followed by a second selective etch stopping on the second layer. A second substrate is attached over the interconnecting part. The electronic components may comprise optoelectronic devices which are illuminated through the second layer.Type: ApplicationFiled: December 9, 2010Publication date: June 16, 2011Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles2) SASInventors: Michel Marty, Didier Dutartre, Francois Roy, Pascal Besson, Jens Prima
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Patent number: 7906381Abstract: A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.Type: GrantFiled: July 3, 2008Date of Patent: March 15, 2011Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Nicolas Loubet, Didier Dutartre, Stéphane Monfray
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Patent number: 7892927Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.Type: GrantFiled: March 16, 2007Date of Patent: February 22, 2011Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Stephane Monfray, Thomas Skotnicki, Didier Dutartre, Alexandre Talbot
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Patent number: 7776745Abstract: A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.Type: GrantFiled: February 9, 2007Date of Patent: August 17, 2010Assignee: STMicroelectronics S.A.Inventors: Nicolas Loubet, Didier Dutartre, Alexandre Talbot, Laurent Rubaldo
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Patent number: 7776679Abstract: A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.Type: GrantFiled: July 18, 2008Date of Patent: August 17, 2010Assignees: STMicroelectronics Crolles 2 SAS, STMicroelectronics S.A.Inventors: Nicolas Loubet, Didier Dutartre, Frederic Boeuf
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Patent number: 7622368Abstract: A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.Type: GrantFiled: February 9, 2007Date of Patent: November 24, 2009Assignee: STMicroelectronics S.A.Inventors: Didier Dutartre, Nicolas Loubet, Alexandre Talbot
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Publication number: 20090032874Abstract: A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.Type: ApplicationFiled: July 3, 2008Publication date: February 5, 2009Applicants: STMICROELECTRONICS SA, STMICROELECTRONICS (Crolles 2) SASInventors: Nicolas Loubet, Didier Dutartre, Stephane Monfray
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Publication number: 20090023275Abstract: A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.Type: ApplicationFiled: July 18, 2008Publication date: January 22, 2009Applicant: STMicroelectronics Crolles 2 SASInventors: Nicolas Loubet, Didier Dutartre, Frederic Boeuf
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Publication number: 20080254580Abstract: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.Type: ApplicationFiled: April 11, 2008Publication date: October 16, 2008Applicant: STMicroelectronics S.A.Inventors: Didier Dutartre, Philippe Coronel, Nicolas Loubet
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Publication number: 20080020532Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.Type: ApplicationFiled: March 16, 2007Publication date: January 24, 2008Applicants: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Stephane Monfray, Thomas Skotnicki, Didier Dutartre, Alexandre Talbot
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Publication number: 20070254450Abstract: A silicon-based single-crystal portion is produced on a substrate selectively in a zone where a single-crystal material is initially exposed. The portion is produced outside other surface zones where the surface of the substrate is made of insulating material. The single-crystal portion is formed from a gas mixture including a silicon precursor of the non-chlorinated hydride type, hydrogen chloride and a carrier gas. The process makes it possible to reduce the temperature at which the substrate has to be heated in order to form the single-crystal portion by selective epitaxial growth.Type: ApplicationFiled: April 18, 2007Publication date: November 1, 2007Applicant: STMicroelectronics S.A.Inventors: Didier Dutartre, Florence Brossard, Benoit Vandelle, Florence Deleglise
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Publication number: 20070254451Abstract: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.Type: ApplicationFiled: April 18, 2007Publication date: November 1, 2007Applicant: STMicroelectronics S.A.Inventors: Didier Dutartre, Laurent Rubaldo, Alexandre Talbot
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Publication number: 20070190787Abstract: A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.Type: ApplicationFiled: February 9, 2007Publication date: August 16, 2007Applicant: STMicroelectronics S.A.Inventors: Nicholas Loubet, Didier Dutartre, Alexandre Talbot, Laurent Rubaldo
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Publication number: 20070190754Abstract: A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.Type: ApplicationFiled: February 9, 2007Publication date: August 16, 2007Applicant: STMicroelectronics S.A.Inventors: Didier Dutartre, Nicolas Loubet, Alexandre Talbot