Abstract: A method of vapor phase epitaxy deposition of silicon on a silicon substrate on or in which exist areas containing dopants at high concentration, among which is boron, while avoiding a selfdoping of the epitaxial layer by boron, including the step of introducing a chlorinated gas, before the epitaxial deposition step, to etch the substrate across a thickness smaller than 100 nm.

Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

Abstract: A method for characterizing a structure including single-crystal silicon-germanium areas on a single-crystal silicon substrate, including the steps of measuring the X-ray diffraction spectrum of the structure, simulating the diffraction spectrum of a single-crystal silicon substrate, simulating the diffraction spectrum of a single-crystal silicon substrate entirely coated with a single-crystal SiGe layer, adding the simulated spectrums while assigning them weights a and 1-a to obtain a sum spectrum, comparing the sum spectrum with the measured spectrum and adjusting the simulation parameters and weight a to reduce the distance between the sum spectrum and the measured spectrum, and after optimizing, adopting the simulation parameters as the measurement parameters.

Abstract: A capacitor integrated on a silicon substrate includes a first electrode made of highly doped polysilicon, a thin silicon oxide layer, a second electrode made of polysilicon and a silicide layer covering the second electrode. The second electrode has a high dopant concentration at its interface with the silicon oxide layer and a low or medium dopant concentration at its interface with the silicide layer.

Abstract: The intrinsic collector of a vertical bipolar transitor is grown epitaxially on an extrinsic collector layer buried in a semiconductor substrate. A lateral isolation region surrounds the upper part of the intrinsic collector and an offset extrinsic collector well is produced. An SiGe heterojunction base lying above the intrinsic collector and above the lateral isolation region is produced by non-selective epitaxy. An in-situ doped emitter is produced by epitaxy on a predetermined window in the surface of the base which lies above the intrinsic collector so as to obtain, at least above the window, an emitter region formed from single-crystal silicon and directly in contact with the silicon of the base.

Abstract: The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

Abstract: The present invention relates to a method of formation of an Si.sub.1-x Ge.sub.x MOS transistor gate where x is higher than 50%, on an silicon oxide gate insulator layer, consisting of depositing an Si.sub.1-y Ge.sub.y layer of thickness lower than 10 nm, where 0<y<30%; and depositing an Si.sub.1-z Ge.sub.z layer of desired thickness, where z>50%. The desired thickness ranges, for example, between 20 nm and 200 nm. x and z range, for example, between 80% and 90%.

Abstract: A method for calibrating the temperature of an epitaxy reactor includes the steps of preparing a reference wafer having undergone on at least one of its surfaces an implant of a doping followed by an activation annealing to form a diffused layer; measuring the sheet resistance of the diffused layer at one point on the surface of the wafer; placing the reference wafer in the epitaxy reactor, the reactor being set at a desired temperature and having a neutral gas flowing therein; and measuring the sheet resistance at the same point and calculating the difference between the two values of sheet resistance, this difference representing the thermal cycle undergone by the reference wafer during its stay in the epitaxy reactor.

Abstract: Method for cleaning, with plasma, the surface of a substrate before another treatment, consisting:in a first cleaning step, in negatively polarizing the substrate and in subjecting it to an argon plasma, andin a second cleaning step, in subjecting the pretreated substrate to a hydrogen plasma, in order to ensure an efficient cleaning of the surface of the substrate.Application to the prior cleaning of a silicon substrate intended to receive an epitaxy.

Abstract: In a method for measuring the flowing of the material, the following steps: forming an array of parallel strips of said material constituting a diffraction grating; submitting said grating at the same conditions as the material, the flowing of which is to be monitored; illuminating the grating by a single wavelength light beam and observing the diffracted light.

Abstract: This process consists of producing patterns (17) of an insulating material on a monocrystalline silicon substrate (12), depositing on the complete structure an amorphous or polycrystalline silicon film (26), covering the latter with a layer (28) of an encapsulating material, carrying out a heat treatment on the structure obtained serving to vertically embed in substrate (12) the insulating material patterns (17) and forming above the latter a monocrystalline silicon layer (33), eliminating the encapsulating material layer (28) and etching the monocrystalline silicon layer obtained (33), so as to form said islands (34).

Abstract: Process for the production of an oriented monocrystalline silicon film with localized defects on an insulating support.This process consists of covering a monocrystalline silicon support of orientation (100) with a SiO.sub.2 layer, producing in the latter a configuration having in the form of oriented (100) parallel insulating strips, an alternation of overhanging parts and recessed parts carrying out the etching of the SiO.sub.2 layer in order to locally form at the ends of said layer at least one opening, said etching being continued until the substrate is exposed, depositing on the etched SiO.sub.2 layer a silicon film, covering the silicon film with an encapsulating layer, carrying out a heat treatment of the structure obtained in order to recrystallize the silicon film in monocrystalline form with the same orientation as the substrate and eliminating the encapsulating layer.