Abstract: A system and method for a radar system are provided. The radar system includes a leader radar device that includes a first clock generation circuit configured to generate a first clock signal, and a first transmitter and receiver configured to transmit and receive radar signals using a first local oscillator signal. The system includes a follower radar device. The follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device. The follower radar device includes a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled, and a second transmitter and receiver configured to transmit and receive first radar signals.

Abstract: A mechanism is provided to reduce interference between vehicular radar systems through communicating radar parameters and physical orientation between vehicles and then using directional information to form clusters of radars, which will have consistent modulation parameters. Radar modulation parameters, such as starting frequency, center frequency, bandwidth, slope, ramp direction, timing, and the like for frequency-modulated continuous-wave (FMCW) radars, are adjusted to reduce or eliminate inter-cluster direct interference between clusters oriented in different directions. For other types of radars, in some embodiments, other operational parameters can be adjusted. In some embodiments, some modulation parameters also can be adjusted to reduce or eliminate intra-cluster indirect interference.

Abstract: An integrated circuit device includes an integrated circuit device die and a substrate. The integrated circuit device die includes a plurality of first contact pads. The first contact pads include a pair of first signal contact pads configured to provide a differential signal port of the integrated circuit device die. The differential signal port is configured to operate at a predetermined frequency. The substrate includes a plurality of second contact pads on a first surface of the substrate. The second contact pads are configured to be soldered to a printed circuit board, and include a pair of second signal contact pads. The integrated circuit device die is affixed to a second surface of the substrate via the first contact pads. The substrate includes a pair of circuit paths that each couple one of the first signal contact pads to an associated one of the second signal contact pads.

Abstract: A transceiver includes a transmitter, a frequency synthesizer coupled to the transmitter, a receiver coupled to the frequency synthesizer and a voltage sensor; and a digital controller coupled to the voltage sensor, the receiver, and the transmitter, wherein based on a DC voltage measurement of an IF signal made by the voltage sensor, a relative phase adjustment occurs of a relative phase associated with a local oscillator (LO) port and a radio frequency (RF) port of the receiver.

Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).

Abstract: A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

Abstract: A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: An example apparatus (100) is for use for use with front-end circuitry (102) to transmit and receive radar wave signals, The apparatus (100) includes digital phase locked loop (PLL) circuitry (104) and a control circuit (106). The digital PLL circuitry (106) provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry (104) includes the DCO circuit (108) which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit (106) controls the selected level of capacitance used by the DCO circuit (108) by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.

Abstract: An example apparatus (100) is for use for use with front-end circuitry (102) to transmit and receive radar wave signals, The apparatus (100) includes digital phase locked loop (PLL) circuitry (104) and a control circuit (106). The digital PLL circuitry (106) provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry (104) includes the DCO circuit (108) which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit (106) controls the selected level of capacitance used by the DCO circuit (108) by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.

Abstract: A transceiver includes a transmitter, a frequency synthesizer coupled to the transmitter, a receiver coupled to the frequency synthesizer and a voltage sensor; and a digital controller coupled to the voltage sensor, the receiver, and the transmitter, wherein based on a DC voltage measurement of an IF signal made by the voltage sensor, a relative phase adjustment occurs of a relative phase associated with a local oscillator (LO) port and a radio frequency (RF) port of the receiver.

Abstract: Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.

Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).

Abstract: A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).

Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: A fast chirp Phase Locked Loop (70) with a phase preset includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit (86) connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current (98) during a start frequency time (302) preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.

Abstract: A fast chirp Phase Locked Loop (70) with a boosted return time includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit (86) connects to the digital controller and the filter. The boost circuit supplies a boost current (98) during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.