Abstract: A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and calculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.

Abstract: A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.

Abstract: A method of calibrating a digitally controlled oscillator (DCO). The method comprises configuring a fine tuning capacitive component of the DCO into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the DCO into a first configuration therefor and determining a resulting first output frequency of the DCO.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal.

Abstract: An integrated circuit for saturation detection comprises: a plurality of gain components; a plurality of saturation detectors with each saturation detector operably coupled to an output of one of the gain components; a plurality of logic elements with a first input of each logic element associated with an output of one of the saturation detectors; and a controller operably coupled to the plurality of logic elements. The controller is arranged to apply a signal to a second input of individual ones of the plurality of logic elements such that an output of the respective logic element identifies a saturation event of the saturation detector associated with that respective logic element.

Abstract: A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, configured to receive the FCW signal and output a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit configured to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and calculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.

Abstract: A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.

Abstract: Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phas

Abstract: A charge pump comprises a charge pump circuit with bipolar switching devices with a common emitter. A collector line which comprises a first current source connects to the high potential provider. An emitter line connects the common emitter to a low potential provider and comprises a second current source. The output is provided by or connected to the collector of the second bipolar switching device and provides said output voltage. A driving stage circuit applies a charge pump circuit driving signal across the bases of the bipolar switching devices and controls the charge pump circuit driving signal in accordance with a driving stage input signal. The driving stage circuit effects a shift of a DC operating point of the charge pump circuit driving signal as an increasing function of the output voltage function of the output voltage of the charge pump circuit.

Abstract: Disclosed is a temperature sensor including a first current generator configured to generate a proportional to absolute temperature (PTAT) current, a second current generator configured to generate an inverse PTAT (IPTAT) current, the PTAT current and IPTAT current being combined to form a reference current having a sensitivity relative to temperature, a plurality of current mirrors to adjust the sensitivity and gain of the reference current, and a variable resistor to set an output calibration voltage based on the generated current.

Abstract: Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phas

Abstract: A phase locked loop circuit includes a voltage controlled oscillator, VCO, configured to receive an oscillator tuning voltage; a phase detector configured to receive an input signal and a reference signal and generate a phase difference pulse signal that is varied in accordance with the oscillator tuning voltage; a loop filter having an input and an output; and a level shifter circuit coupled to an output of the phase detector and the loop filter input and configured to apply a level shift to the phase difference pulse signal such that the level shift is configured to compensate VCO gain and the loop filter averages the phase difference pulse signal to output an averaged signal to the VCO.

Abstract: A circuitry for and a method of generating a frequency modulated radar transmitter signal are provided. The circuitry comprises a modulation signal generator for generating a modulation signal having a waveform describing a required frequency modulation of the frequency modulated radar transmitter signal and comprises a PLL circuitry for generating the frequency modulated radar transmitter signal in dependence of the modulation signal. In the PLL circuitry a controllable frequency divider controls the output frequency of the PLL circuitry in dependence of the modulation signal. The PLL circuitry further comprises a phase detector, a controllable oscillator and possibly a low pass filter. The PLL circuitry further comprises a calibration circuitry being configured to control a parameter of at least one of the phase detector and the controllable oscillator to maintain a loop gain of PLL circuitry.

Abstract: An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. A control circuit coupled to one or more control inputs of the capacitive divider and controllable capacitor bank is configured to modify the equivalent capacitance of the capacitive divider and the controllable capacitor bank for providing capacitance steps, each capacitance step being variable over frequency such that for each step a frequency change ?f of the frequency characteristic is maintained constant in the linearization frequency range.