Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

Abstract: A memory controller and method for interleaving volatile and non-volatile memory different latencies and page sizes are described wherein a single DDR3 memory controller communicates with a number of memory modules comprising of at least non-volatile memory, e.g., spin torque magnetic random access memory, integrated in a different Rank or Channel with a volatile memory, e.g., dynamic random access memory (DRAM).

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of thermal selectable memory cells, each memory cell being connected to a conductive line, the conductive line having a first portion for applying a heating current, and a second portion for applying a programming current. The integrated circuit is configured such that the heating current and the programming current can be routed respectively to the first and the second portion of the conductive line independently from each other.

Abstract: According to one embodiment of the present invention, an integrated circuit includes a plurality of resistivity changing memory cells, each memory cell including a top electrode, a bottom electrode and resistivity changing material being disposed between the top electrode and the bottom electrode. The top electrodes together form a continuous common first electrode. Alternatively, a first continuous common electrode which is electrically connected to all top electrodes is disposed above the top electrodes. A second electrode connectable to a fixed potential is disposed above the first electrode such that the first electrode and the second electrode together form a capacitor.

Abstract: An integrated circuit device and a method for providing distributed voltage regulation. The device includes a plurality of memory cell arrays and access circuitry dependent on one or more regulated voltages generated on the device and a plurality of pulsed digital distributed output units configured to generate the one or more regulated voltages. The device also includes a voltage regulator control logic configured to generate one or more control signals to control the distributed output units based, at least in part, on a comparison between one or more reference voltages and the one or more regulated voltages.

Abstract: A memory cell is disclosed. The memory cell comprises a storage element including a first terminal and a second terminal, and a select transistor including a first terminal, a second terminal and a control terminal. The voltage at the control terminal of the select transistor affects a current flowing between the first terminal and the second terminal. The first terminal of the select transistor is coupled to the second terminal of the storage element. A bit line is coupled to the first terminal of the storage element, a first word line is coupled to the control terminal of the select transistor, and a second word line is coupled to the second terminal of the select transistor.

Abstract: An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

Abstract: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.

Abstract: A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.

Abstract: A memory with memory cells, wherein a memory cell includes a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches include control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able to change the resistance depending

Abstract: In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field, which is higher or lower than the first magnetic field, is applied to the magneto resistive memory cell. It is then determined whether the magneto resistive memory cell meets a programming criterion. The magnetic field is increased or decreased in case that the magneto resistive memory cell does not meet the programming criterion until the magneto resistive memory cell meets the programming criterion.

Abstract: An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamping device coupled between the second input of the voltage comparator and a second input signal node, a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, and a sensing scheme including an actively balanced capacitance coupled to the source and drain of the second transistor.

Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

Abstract: A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of the applied current or voltage is determined in proportion to the measured resistance of the memory cell so as to result in a predefined level of power dissipation within the memory cell, said dissipated power operable to heat the memory cell.

Abstract: The present invention relates to a memory with memory cells, wherein a memory cell comprises a resistive element and a switch, wherein the memory cells are connected with a common plate line and with respective bit lines, wherein the common plate line supplies a plate voltage, wherein the switches comprise control inputs that are connected with word lines for controlling the switching states, wherein the word lines are connected with a word line driver that supplies selected word lines with a voltage, wherein the bit lines are connected with second switches, wherein the first bit lines are connectable by respective second switches with a first voltage level and the second bit lines are connectable by respective second switches with a second voltage level, wherein a first and a second bit line are connectable as a bit line pair with a sense amplifier, wherein the sense amplifier amplifies a voltage difference between the first and the second bit line of the bit line pair, wherein the resistive element is able

Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Abstract: A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first and a second input terminal. A switching circuit is configured to connect each of the cell columns to the first input terminal and the pair of reference cell columns coupled in parallel to the second input terminal, and configured to connect the first reference cell column to the first input terminal and the second reference cell column to the second input terminal.

Abstract: A design for a memory array that uses bi-directional write currents and that avoids switched ground connections for memory cells, thereby reducing signal loss and noise problems is described. Positive and negative current sources are provided to supply the bi-directional current that is used to write to a memory cell. These current sources may be selectively connected to bit lines that are electrically connected to the memory cells. Applying a positive current, from the positive current source, through a memory cell writes a “1”, and applying a negative current, from the negative current source, through a memory cell writes a “0”. Use of both a positive and a negative current source enables writing to the memory cells without relying on a switched ground connection to provide bi-directional current. This permits a ground connection of each memory cell to be connected to a fixed ground. An example in which this design is used with a spin injection magneto-resistive random access memory (MRAM) device is shown.