Abstract: An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.

Abstract: A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

Abstract: An apparatus comprising a magnetically shielded MRAM chip and a method of manufacturing the same. The apparatus includes an MRAM module and a protective cover. The MRAM module includes a circuit board and a memory chip attached to the circuit board, the memory chip containing magnetoresistive random access memory (MRAM) cells. The protective cover includes a magnetic shielding material and at least partially encloses the memory chip. In another embodiment, the protective cover shields the memory chip without shielding at least a portion of the circuit board.

Abstract: An apparatus comprising a magnetoresistive random access memory (MRAM) and a method of forming the same. The apparatus includes a memory circuit comprising an MRAM cell, and a charge pump circuit electrically coupled to the memory circuit wherein the memory circuit and at least a first portion of the charge pump circuit are fabricated on a single semiconductor chip. The charge pump circuit further includes a second portion comprising at least one capacitor external to the semiconductor chip. The second portion of the charge pump circuit may be packaged in a chip package or external to the chip package.

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

Abstract: An MRAM memory chip includes a plurality of magnetoresistive memory cells each including a magnetic tunnel junction having first (fixed) and second (free) magnetic regions, where the second magnetic region includes at least two ferromagnetic layers that are antiferromagnetically coupled, wherein a coil surrounds the memory chip for creating a magnetic offset field. Further, a method of writing to an MRAM chip includes bringing the memory cells into an active state exhibiting a reduced switching field before writing thereto and bringing the memory cells into a passive state exhibiting enlarged switching field after writing thereto.

Abstract: A current sense amplifier including clamping devices and a current mirror is configured to sense the resistance of an MTJ memory cell utilizing a bitline boost circuit to shorten the charging time for parasitic circuit capacitance. The bitline boost circuit includes a source follower coupled to a reference voltage and a switch coupled to another voltage source. The switch is enabled to conduct during an initial period of sensing the resistance of the memory cell. The source follower in the bitline boost circuit is configured to clamp the voltage of an input signal at substantially the same level as the clamping devices, and to provide additional current to shorten the period for charging parasitic capacitance. The resulting current sense amplifier can be used to implement a memory device with fast and reliable read times and low manufacturing cost.

Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

Abstract: A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors.

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

Abstract: A magneto-resistive random access memory (MRAM) array comprises global bit lines segmented using a plurality of local bit lines. A read/write controller is connected to the switches. Switches couple the global bit line to the local bit lines. The MRAM array has low leakage currents and facilitates a high signal-to-noise (S/N) ratio of read and write operations.

Abstract: A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.

Abstract: A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.

Abstract: A memory sense amplifier for a semiconductor memory device is provided with a compensation current source device that generates a compensation current and feeds it to an interconnected bit line. The compensation current is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device on the selected and interlinked bit line device that is substantially constant over time.

Abstract: In a method for operating an MRAM semiconductor memory configuration, for the purpose of reading an item of stored information, reversible magnetic changes are made to the TMR cell and a current that is momentarily altered as a result is compared with the original read signal. As a result, the TMR memory cell itself can serve as a reference, even though the information in the TMR memory cell is not destroyed, i.e. writing-back does not have to be effected. The method can preferably be applied to an MRAM memory configuration in which a plurality of TMR cells are connected, in parallel, to a selection transistor and in which there is a write line which is not electrically connected to the memory cell.

Abstract: The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches.

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors.

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches.