Patents by Inventor Dinesh Kumar Agarwal

Dinesh Kumar Agarwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11204722
    Abstract: A content-aware storage system and method for use therewith are presented. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive an image; determine an amount of spare memory space; generate a lower-resolution version of the image, wherein a resolution level of the lower-resolution version of the image is based on the determined amount of spare memory space; and store the image and the lower-resolution version of the image in the memory. Other embodiments are provided.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: December 21, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20210382621
    Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
  • Publication number: 20210382650
    Abstract: A content-aware storage system and method for use therewith are presented. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive an image; determine an amount of spare memory space; generate a lower-resolution version of the image, wherein a resolution level of the lower-resolution version of the image is based on the determined amount of spare memory space; and store the image and the lower-resolution version of the image in the memory. Other embodiments are provided.
    Type: Application
    Filed: June 4, 2020
    Publication date: December 9, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20210382652
    Abstract: Aspects of a storage device including a plurality of dies and a controller are provided which allow for asymmetric die operation handling so that controller overheads associated with common resource intensive operations may be incurred in the background without delaying subsequent die operations. When the controller receives a command to perform an MLC operation such as programming a number of dies, the controller refrains from performing the MLC operation in one or more of the dies for a period of time while simultaneously performing the MLC operation in a remainder of the dies. Instead, the controller performs another operation, such as an SLC operation, another MLC operation, or a transfer operation, that involves a common resource in these dies during the period of time. Controller overheads associated with these other operations thus are incurred without creating bottlenecks when the number of dies is large, thereby improving storage device performance.
    Type: Application
    Filed: June 8, 2020
    Publication date: December 9, 2021
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal
  • Patent number: 11194482
    Abstract: A storage system and method for segregating outliers in a virtualization system are presented. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to track a write amplification caused by each of a plurality of virtual machines; determine that a write amplification of one of the plurality of virtual machines is outside of an acceptable write amplification range; and perform a corrective action to reduce write amplification of the one of the plurality of virtual machines. Other embodiments are provided.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: December 7, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20210374176
    Abstract: A storage system and method for host-assisted memory block color coding for faster media search are provided. In one embodiment, a controller of the storage system is configured to receive an image and color properties of the image from a host and store the image in an area of memory associated with the color properties. Other embodiments are provided.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20210373782
    Abstract: A storage system and method for segregating outliers in a virtualization system are presented. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to track a write amplification caused by each of a plurality of virtual machines; determine that a write amplification of one of the plurality of virtual machines is outside of an acceptable write amplification range; and perform a corrective action to reduce write amplification of the one of the plurality of virtual machines. Other embodiments are provided.
    Type: Application
    Filed: June 2, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventor: Dinesh Kumar Agarwal
  • Publication number: 20210373789
    Abstract: A storage system, host, and method for optimizing storage of a sequence of images are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive, from a host, common image data that is shared by a plurality of images and delta image data that is different in each of the plurality of images; store the common image data and the delta image data in the memory; and create a map for the plurality of images, wherein each image of the plurality of images maps to a memory location of at least a part of the common image data and to a memory location of that image's delta image data. Other embodiments are provided.
    Type: Application
    Filed: May 29, 2020
    Publication date: December 2, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20210326172
    Abstract: A storage system and method for multiprotocol handling are provided. In one embodiment, a computing device is provided comprising a plurality of communication channels configured to communicate with a storage system, wherein a first communication channel has a faster data transfer speed than a second communication channel. The computing device also comprises a processor configured to determine a priority level of a command; send the command with an indication of its priority level to the storage system; in response to the command being a high-priority command, use the first communication channel for transferring data for the command; and in response to the command being a low-priority command, use the second communication channel for transferring data for the command. Other embodiments are provided.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 11138071
    Abstract: On-chip XOR parity data management combines storage blocks in non-volatile memory. Multiple source storage blocks are selected to be combined and stored into a destination storage block. Each source storage block includes a data section and a parity section. The parity section includes XOR parity data that enables data recovery of physical pages of the source storage block. The source storage blocks are merged into the destination storage block, which is configured to store multiple bits per memory cell. Parity sections of one or more of the plurality of source storage blocks remain unchanged after merging into the destination storage block.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 5, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dinesh Kumar Agarwal, Amit Sharma
  • Publication number: 20210157522
    Abstract: An apparatus includes a plurality of memory die and a controller coupled to the plurality of memory die. The controller is configured to selectively process a plurality of random read commands in such a way to reduce a total time required to execute the random read commands.
    Type: Application
    Filed: November 27, 2019
    Publication date: May 27, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Abhinandan Venugopal, Amit Sharma, Dinesh Kumar Agarwal
  • Publication number: 20210149583
    Abstract: Aspects of a storage device are provided which allow for identification of control page patterns from previous read commands and prediction of control pages to load in advance for subsequent read commands. The storage device includes a memory configured to store data and a plurality of control pages. Each of the control pages includes a plurality of logical addresses associated with the data. A controller is configured to receive from a host device a plurality of read commands associated with a sequence of the control pages. The controller is further configured to identify and store a control page pattern based on the sequence of control pages and to predict one or more of the control pages from one or more of the other control pages in the sequence in a subsequent plurality of read commands.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Dinesh Kumar Agarwal, Hitesh Golechchha, Sourabh Sankule
  • Publication number: 20210109654
    Abstract: Aspects of a storage device are provided which allow a read command to be identified for execution from multiple read commands received from a host. The storage device includes a memory configured to store a plurality of data units each comprising one or more data fragments, and metadata associated with the data units. A controller is configured to receive from the host a plurality of read commands each requesting one of the data units. The controller is further configured to identify one of the read commands based on the metadata, and to transfer the data unit associated with the identified read command to the host before transferring the data unit associated with the other read commands.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 15, 2021
    Inventor: Dinesh Kumar AGARWAL
  • Patent number: 10963592
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: March 30, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Publication number: 20200250346
    Abstract: A memory device operable in either of a Secure Digital operational mode and an NVMe operational mode includes password conversion logic to enable the memory device user-mode memory blocks to be accessed in the NVMe operational mode after the memory device was locked in the Secure Digital operational mode.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 6, 2020
    Inventors: Vinod Sasidharan, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 10055267
    Abstract: In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: August 21, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Dinesh Kumar Agarwal, Ramkumar Ramamurthy, Vijay Sivasankaran
  • Publication number: 20160259570
    Abstract: In a non-volatile memory system, such as flash memory, when selecting a block for write operation, the system selects blocks from a free block list (FBL). The memory circuits of non-volatile systems often experience cluster failures, where multiple blocks of a physical region are bad. If the free block list is loaded with blocks from a region having a cluster failure, this can result in multiple back to back write errors. To help avoid this situation, the blocks of a memory array are divided into physical zones and, when selecting blocks to replenish the free block list, blocks are chosen cyclically from the zones.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 8, 2016
    Inventors: Dinesh Kumar Agarwal, Ramkumar Ramamurthy, Vijay Sivasankaran